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More than Moore technologies for next generation computer design
Topaloglu R., Springer Publishing Company, Incorporated, New York, NY, 2015. 218 pp. Type: Book (978-1-493921-62-1)
Date Reviewed: Jul 2 2015

This year, we are celebrating the 50-year anniversary of Moore’s law. On April 19, 1965, Gordon Moore published a four-page paper titled “Cramming more components onto integrated circuits.” This paper made a prediction about the number of components in integrated circuits, which we translate now as the number of transistors per chip. This prediction, known as Moore’s law, states that this number will double every year, then 18 months, and finally will stabilize at two years. After five decades, this prediction still holds, acting as the strategic target of all high-tech companies. However, we are about to kiss the law goodbye. Given that we already have 18nm technology (the Intel Broadwell central processing unit (CPU), for example), additional advances in process technology for metal-oxide semiconductors (MOSs) become more expensive, give diminishing returns, and are very unreliable. The current question is: How can we get more performance (and less power consumption, more reliability, and the list goes on and on) without Moore’s law? This book contains several answers. These answers are by no means conclusive or exhaustive, but they are very good indications of where we can look for solutions.

The three answers, or possible answers, presented are 3D stacking, memory design and architecture, and photonic interconnection. With the slowing down and eventual end of Moore’s law, we can no longer depend on scaling transistors down. The solution is similar to big cities when they run out of land; they go vertical, like Manhattan, for example. 3D stacking technology builds chips as floors (3D) instead of the usual 2D chips we have. Two major performance bottlenecks are memory systems and interconnections. This is why these two items are answers number 2 and 3 in this book after 3D stacking.

The first two chapters discuss 3D integration (also known as 3D stacking in many publications). Chapter 1 discusses the positive and negative effects of through-silicon vias (TSVs). TSVs are the vertical connections among the 3D layers. Those connections have non-negligible area, power overhead, and delay. Therefore, TSVs constitute a major factor of 3D stacking benefits. Chapter 1 is a good overview of TSV overhead and how to overcome it. Chapter 2 takes a more holistic view of the whole 3D chip and not just TSVs. It discusses different approaches to modeling electrical and thermal behavior of 3D chips. Then, the chapter concludes with an interesting section about future 3D chip architecture.

The following four chapters are dedicated to memory design and architecture. Memory systems have been a major performance bottleneck since the single-core era. This is why the term “memory wall” has been coined since 1995. On the design part, spin-transfer torque magnetic RAM (STT-MRAM) is discussed in detail as a viable substitution for traditional last-level cache SRAM, despite the relatively high write energy of STT-MRAM. The theory behind STT-MRAM, its modeling, and circuit failure analysis are discussed in chapter 3. More discussion about STT-MRAM is presented in chapter 4. There are some repetitions from chapter 3; however, the chapter contains more analysis. Chapter 5 complements the previous two chapters by discussing reliability issues with STT-MRAM and how thermal and process variations affect soft errors. On the architecture side, chapter 6 presents a more holistic view of traditional memory (that is, dynamic RAM, or DRAM) by providing new DRAM architectures and interfaces that allow better integration of DRAM with the rest of the system. The chapter also discusses how to integrate DRAM with other nonvolatile memory (pulse code modulation (PCM) is discussed here) to get the best of both worlds. The whole discussion revolves around performance (we need higher and more predictable performance), capacity, and cost.

Finally, the last two chapters discuss photonics interconnection. Chapter 7 presents a photonic network on chip (NoC), called LumiNOC, optimized for performance and power. Chapter 8 looks at design automation for photonic systems as a good first step toward fully automated design.

This is an edited book, so readers will get to see different perspectives. All of the chapters are extended versions of published papers (or combinations of several papers). Some of the chapters (the first five) require a solid background in circuits and very large-scale integration (VLSI).

The conclusion is that advances after Moore’s law must be accomplished at all layers of the computing stack, from algorithms to programming, to architecture to circuits, all the way down to process technology.

Reviewer:  Mohamed Zahran Review #: CR143579 (1509-0739)
1) Moore, G. Cramming more components onto integrated circuits. Electronics 38, 8(1965), 114–117.
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