Computing Reviews
Today's Issue Hot Topics Search Browse Recommended My Account Log In
Review Help
Search
Architectural support for data-driven execution
Matheou G., Evripidou P. ACM Transactions on Architecture and Code Optimization11 (4):1-25,2015.Type:Article
Date Reviewed: Apr 22 2015

Although various approaches for data-driven execution exist, the authors focus on data-driven multithreading (DDM), following up on their previous work in that area. This interesting paper deals with the low-level details of building a complete system for data-driven execution. The paper represents an advance in the state of the art for DDM as the authors move from simulation to actual prototyping on a field-programmable gate array (FPGA).

DDM divides the code to be executed at a fine grain into threads. These threads are then scheduled as soon as their input data is available, setting up a producer/consumer relationship between the threads. The approach taken by the authors is to either use manual annotation or a source-to-source compiler supporting higher-level pragmas to extract such threads (termed d-threads) from the program. The final target is a program with DDM-related annotations with mnemonics defined by the authors in the paper. A frequent pattern that occurs in their examples is transforming different independent loop iterations into d-threads. The core contribution of the paper is an entire FPGA prototype that can execute these d-threads by tracking their dependencies and scheduling them when ready on a multicore. At the core of the implementation is the thread-scheduling module. This module uses memory to maintain the startup contexts of threads and their dependencies and finite-state machines (FSMs) to decide when threads become ready to execute, at which point they are dispatched to multicores. The results obtained are impressive with near perfect speedups.

In general, the paper is an interesting read, particularly for an audience that is interested in prototyping novel ideas in computer architecture on FPGAs.

Reviewer:  Amitabha Roy Review #: CR143374 (1507-0586)
Bookmark and Share
 
Parallel Architectures (C.1.4 )
 
 
Gate Arrays (B.7.1 ... )
 
 
Threads (D.4.1 ... )
 
 
Concurrent Programming (D.1.3 )
 
Would you recommend this review?
yes
no
Other reviews under "Parallel Architectures": Date
A chaotic asynchronous algorithm for computing the fixed point of a nonnegative matrix of unit spectral radius
Lubachevsky B., Mitra D. Journal of the ACM 33(1): 130-150, 1986. Type: Article
Jun 1 1986
iWarp
Gross T., O’Hallaron D., MIT Press, Cambridge, MA, 1998. Type: Book (9780262071833)
Nov 1 1998
Industrial strength parallel computing
Koniges A. Morgan Kaufmann Publishers Inc., San Francisco, CA,2000. Type: Divisible Book
Mar 1 2000
more...

E-Mail This Printer-Friendly
Send Your Comments
Contact Us
Reproduction in whole or in part without permission is prohibited.   Copyright 1999-2024 ThinkLoud®
Terms of Use
| Privacy Policy