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RIVER: reconfigurable flow and fabric for real-time signal processing on FPGAs
Brugger C., Hillenbrand D., Balzer M. ACM Transactions on Reconfigurable Technology and Systems7 (3):1-16,2014.Type:Article
Date Reviewed: Oct 14 2014

Field-programmable gate arrays (FPGAs) have become the most effective, powerful, and generic logic design and verification tools during the last decade. Specialized hardware implementations for building high-performance parallel processing capabilities are a key application for which FPGAs are gaining momentum.

The authors contribute a parallel dataflow-oriented architecture called RIVER. A cloud-based online FPGA design flow is depicted that utilizes “a repository of precompiled dynamic streaming engine processors (DSEs)”; building blocks based on the architecture are also presented. The online design space can be searched and instantiated within a fraction of seconds. The authors show that "applications from image processing and financial mathematics can be mapped efficiently to multicore DSEs." Furthermore, a comparison of an eight-core DSE example to “existing highly optimized signal and graphics accelerators” is presented, which shows that the “multicore DSE example designs are competitive in terms of power and performance when compared to commercially available signal processors and graphics accelerators ([graphics processing units,] GPUs).”

Based on the examples shown in the paper, it is evident that the proposed technique can be effectively utilized for implementing an arbitrary combination of digital image processing or signaling filters. The mathematical solution for the market share decision process highlights another aspect: a complex problem may still need customized effort such as the design of a square root calculation block. However, the concept of building an online repository and using it to minimize design effort and time for FPGAs is quite interesting, and understandably the repository can grow over time to support a wide range of solutions.

Reviewer:  Mohammed Ziaur Rahman Review #: CR142826 (1501-0059)
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Real-Time And Embedded Systems (C.3 ... )
 
 
Data-Flow Architectures (C.1.3 ... )
 
 
Domain-Specific Architectures (D.2.11 ... )
 
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