Digital circuits where the output values depend on the state of the system are called sequential. A finite state machine (FSM) is a modeling technique for sequential circuits. At any point of its operation, the machine will be in one of a finite number of possible states.

Given a state and input values, the model can be used to determine the output values of the circuit, and the possible next states that the system can transition into. An FSM where the output depends only on the present state is said to be of Moore type. When the FSM output depends on both the input and the present state, it is called a Mealy type machine.

State machines where all of the transitions occur under the control of a clock signal are called synchronous FSMs. When a state machine directly reacts to the changes in the environment, and the state transitions can happen independent of any clock signal, such a machine is called an asynchronous state machine. This book covers synchronous FSMs only.

Transitions in a synchronous FSM can be of various types. Unconditional transitions are the simplest and represent changes that can happen at the next clock. Conditional transitions depend on an input for the change to take place at the next clock. Timed transitions are those that only depend on a timer, and the change happens after a specified number of clock cycles. Conditional timed transitions are those that depend on a timer along with an actual input.

Pedroni introduces a new classification of FSMs, with three categories based on the transition type and the nature of the outputs. Regular (pure) state machines have only untimed transitions and outputs do not depend on previous output values. Timed state machines have one or more transitions that depend on time, but still have outputs that do not depend on past output values. Recursive state machines have one or more outputs that depend on the past output values, and the transitions can be timed.

Thus, in order to implement a synchronous FSM into hardware, two important decisions need to be made. The first is the state machine category--regular, timed, or recursive--and the second is about the type--Moore or Mealy. The book describes the theory and design of FSMs for all of these categories, and provides complete examples in VHDL and SystemVerilog.

The material is well organized and makes the book suitable for both students and practitioners. Various exercises at the end of the chapters can help students enhance their learning, and the various design tips provide guidance to engineers in the industry.

The first four chapters are introductory. A range of topics like FSM basics, synchronization schemes, glitch elimination, state encoding, deadlock avoidance, machine factoring, and data path control are all covered briefly, but without missing any essentials. Classical design mistakes are also presented. The importance of state transition diagrams is emphasized.

Chapters 5 through 7 describe regular state machines. Various examples like counter, parity detector, and different controllers that occur in practice are presented. Exercises, especially in chapter 5, provide further insight into other applications, including an arbiter and Manchester encoders. The focus of chapters 6 and 7 is on register transfer logic (RTL) implementation. These chapters also provide some basics on VHDL and SystemVerilog.

Timed state machines are covered in chapters 8 through 10. Such state machines contain a timer where the time is measured in number of clock cycles. An example application is a controller for a blinking light that needs to be on and off for a specific number of cycles. Switch debouncers, traffic light controllers, and password detectors are examples of circuits that can use a timed state machine. There is a specialization here for a family of circuits where the output goes up or down after a certain number of clock edges following an input trigger. Pulse shifters and pulse stretchers are particular cases in this family that are considered. Chapters 9 and 10 focus on the RTL implementation.

Recursive state machines are covered in chapters 11 through 13. An example is a long string comparator where the machine must determine whether the last N bits are pairwise equal. Such machines need auxiliary registers to keep previous values. Sequential multipliers and dividers are similar examples in this category, and are described in chapter 11, along with other applications. Chapters 12 and 13 focus on RTL implementation.

Chapter 14 provides additional design examples where all three FSM categories are used. The generic FSM design approach proposed in the book is demonstrated again here, along with complete RTL code.

Chapter 15 briefly explores an alternative approach to FSM design in which a counter serves as a pointer to a lookup table (LUT). A simpler circuit will not always result, and the encoding choices may be restricted in this methodology.

Overall, the book is very impressive. It is up to date with the latest hardware FSM needs and presents a classification that is suitable for formulating the design steps into a standard strategy. The discussion is very detailed and comprehensive, and the provided RTL examples are readily deployable.

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