This paper discusses what is driving system-on-a-chip (SOC) development, and analyzes the current design process for achieving the right design at the right time. The analysis includes not only the traditional register-transfer level (RTL) to layout design flow, but also what it takes to get samples, and to ramp-up volume production, at the right time. Without major improvements to the process, designers will find themselves working harder just to maintain the status quo. The author summarizes the main issues, and suggests which ones need the most attention.

Overall, the paper is well organized and well written. Taken from a keynote speech at the Second Institute of Electrical and Electronics Engineers (IEEE) International Symposium on Quality Electronic Design, it is targeted toward readers in the electronic design and test community. While the author draws from his experiences at STMicroelectronics, the discussion applies to the design process in general. Most readers who work on SOC design will see, or have seen, the same problems.

Although the paper was published in 2002, it is relevant today; many of the issues are still present in the design process. This paper will be useful for anyone who may be starting to design SOCs, or who wants an overview of what it takes to get a design to market in complementary metal-oxide semiconductor (CMOS) 0.18 micron technology.