Computing Reviews
Today's Issue Hot Topics Search Browse Recommended My Account Log In
Review Help
Search
Interconnect-power dissipation in a microprocessor
Magen N., Kolodny A., Weiser U., Shamir N.  System level interconnect prediction (Proceedings of the 2004 international workshop, Paris, France, Feb 14-15, 2004)7-13.2004.Type:Proceedings
Date Reviewed: May 7 2004

This paper discusses the important issue of power dissipation in the design of high-performance microprocessors. Its major focus is on dynamic power consumption due to the switching of capacitors, and on the role of the interconnect power in this. The authors performed interconnect power analysis on a state-of-the-art microprocessor, made up of 77 million transistors in 130nm technology. The analysis was based on a stochastic dynamic power estimation method.

For the purpose of the analysis, the authors considered the signal interconnect lengths between the drivers and receivers, but did not include the global clock grid. However, the capacitances included all types of capacitive loads, including the diffusion capacitances of the drivers, capacitances of the metal wiring, and the gate load of the receivers. Repeater gate and diffusion capacitances were also added to the original net. Metal capacitances included cross-capacitances between the nets, with the unit miller coupling factor (MCF).

The results of the analysis indicate that interconnect switching accounts for about half of the total dynamic power consumption. The net topologies were split into two parts, namely, local and global nets. The local net was typically observed to have 30 percent higher fan out, and about 80 percent smaller interconnect capacitance, compared to the global net. However, as observed in the paper, the interconnect power was divided almost equally between the local and the global nets, due to the larger number of local nets. Ninety percent of the dynamic power was consumed by ten percent of the nets, and power reduction for these nets thus appeared to be the most demanding.

The authors end by suggesting some methods to implement power-aware routing. One vital suggestion was to reduce capacitances, possibly via interconnect length reduction, and via increased spacing between routing wires. As a possible extension of an existing industrial router, based on rip-up and reroute, some of the nets were classified as power-critical nets, and rip-up of these nets was of the lowest priority. Some potential future work is also discussed.

Reviewer:  Parthasarathi Dasgupta Review #: CR129567 (0411-1343)
Bookmark and Share
  Reviewer Selected
 
 
Microprocessors And Microcomputers (B.7.1 ... )
 
 
Placement And Routing (B.7.2 ... )
 
Would you recommend this review?
yes
no
Other reviews under "Microprocessors And Microcomputers": Date
Microprocessors and programmed logic (2nd ed.)
Short K., Prentice-Hall, Inc., Upper Saddle River, NJ, 1987. Type: Book (9789780135806067)
Nov 1 1987
The Motorola 68020
Zoch C., McGraw-Hill, Inc., New York, NY, 1986. Type: Book (9789780070425859)
Sep 1 1988
Digital electronics with microprocessor applications
Dixon A., Antonakos J., John Wiley & Sons, Inc., New York, NY, 1987. Type: Book (9789780471890188)
Dec 1 1988
more...

E-Mail This Printer-Friendly
Send Your Comments
Contact Us
Reproduction in whole or in part without permission is prohibited.   Copyright 1999-2024 ThinkLoud®
Terms of Use
| Privacy Policy