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Cache-coherent multiprocessors
Baskett F., University Video Communications, Stanford, CA, 1991. Type: Book
Date Reviewed: Feb 1 1994

In this videotaped lecture, Baskett presents the case for multiprocessors generally and cache-coherent designs specifically. The lecture is based on the cache design of the Silicon Graphics Power series logical and physical design, which started in October 1986. Topics covered include justification of multiprocessing and cache coherence, design goals for the Power series, options for cache designs, bus bandwidth considerations, and results.

Baskett lays effective groundwork to justify multiprocessing in terms of both technological advances and processing requirements. He argues for cache coherence based on simplifying the programming model (shared memory) for multiprocessors, costs that are lower than high-performance main memory, and added bandwidth available to private caches. He presents an effective discussion of performance measures in developing the performance design goals for the Power series based on Livermore Kernels and Linpack benchmarks and considers the tradeoffs between write-through and snoopy caches. In the end, both write-through (at the second-level cache) and snooping at the first level are implemented, resulting in less-than-expected bus bandwidth requirements based on traditional models. The final design is reviewed in terms of bandwidth requirements, benchmark performance, and scalability as technology moves.

The strength of this work is the technical content, which suffers from the heavy use of artificial benchmarks but is generally well done. In addition, Baskett makes fair use of graphics to enhance what is basically a wooden lecture with the camera trained on the head and shoulders. The presentation is well-punctuated with “uh”s, and the expression “in fact” is overused to distraction. Additional graphics and a more animated presentation would significantly enhance the presentation.

While not must viewing, this tape remains a good, simply stated argument for cache-coherent multiprocessors, punctuated with design insights. I recommend it, but you should watch it early in the evening, since it can lull you to early sleep with its pace and style.

Reviewer:  Robert E. Mahan Review #: CR116257
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Multiple Data Stream Architectures (Multiprocessors) (C.1.2 )
 
 
Cache Memories (B.3.2 ... )
 
 
Performance of Systems (C.4 )
 
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