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	Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming Vemuri R., Kalyanaraman R. IEEE Transactions on Very Large Scale Integration (VLSI) Systems3(2):201-214,1995.Type:Article     Published By: IEEE Educational Activities Department       Use your personal or institutional subscription to read the fulltext of the article.               You can purchase an article without having a subscription.
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