| |
Browse All Reviews > Hardware (B) > Integrated Circuits (B.7) > Design Aids (B.7.2) > Verification (B.7.2...)
|
|
 |
|
|
| |
|
|
| |
1-7 of 7
Reviews about "Verification (B.7.2...)":
|
Date Reviewed |
| |
Advanced formal verification
Drechsler R. (ed), Kluwer Academic Publishers, Norwell, MA, 2004. Type: Book (9781402077210)
This book is best described as a collection of independent papers that describe experimental tool development and/or current research projects in the field of formal verification. It will be a good starting point for those contemplatin...
|
Feb 17 2005 |
| |
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification
Adir A., Almog E., Fournier L., Marcus E., Rimon M., Vinov M., Ziv A. IEEE Design & Test of Computers 21(2): 84-93, 2004. Type: Article
In software engineering, “verification” refers to the requirement that a program must generate acceptable results for all valid inputs or initial states. The functional specification defines the function that a prog...
|
Dec 20 2004 |
| |
Classification of defective analog integrated circuits using artificial neural networks
Stopjaková V., Malošek P., Mičušík D., Matej M., Margala M. Journal of Electronic Testing: Theory and Applications 20(1): 25-37, 2004. Type: Article
The simulation results of applying the theory of artificial neural networks (ANN) to the problem of detecting catastrophic defects injected into a two-stage operational amplifier are presented in this paper....
|
Oct 7 2004 |
| |
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions
Jain J., Bitner J., Abadir M., Abraham J., Fussell D. IEEE Transactions on Computers 46(11): 1230-1245, 1997. Type: Article
Verifying the circuit implementation of Boolean functions against their abstract specifications is a fundamental and difficult problem in circuit design. This paper presents a graph-theoretical representation, the indexed binary decisi...
|
Jul 1 1998 |
| |
Automatic generation of functional vectors using the extended finite state machine model
Cheng K., Krishnakumar A. ACM Transactions on Design Automation of Electronic Systems 1(1): 57-79, 1996. Type: Article
Researchers and designers working on software tools for automatic generation of functional vectors for sequential circuits are this paper’s main audience. Unlike similar research for combinational circuits, which has traditio...
|
Apr 1 1997 |
| |
Design and verification of the Rollback Chip using HOP: a case study of formal methods applied to hardware design
Gopalakrishnan G., Fujimoto R. ACM Transactions on Computer Systems 11(2): 109-145, 1993. Type: Article
The advantages and disadvantages of top-down hardware design methodologies based on the formal verification of transitions to subsequent design steps are illustrated in detail. The methodology is illustrated on a nontrivial example: a ...
|
Jul 1 1994 |
| |
Trace theory for automatic hierarchical verification of speed-independent circuits
Dill D., MIT Press, Cambridge, MA, 1989. Type: Book (9789780262041010)
The speed-independent circuits of the title are circuits without clocks that satisfy specifications without assumptions about the relative speed of components. Some general claims are made (on the back cover) that such circuits ...
|
Jan 1 1992 |
| |
|
|
| |
|
|
