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Browse All Reviews > Hardware (B) > Integrated Circuits (B.7) > Design Aids (B.7.2) > Placement And Routing (B.7.2...)
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1-10 of 26
Reviews about "Placement And Routing (B.7.2...)":
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MaizeRouter: engineering an effective global router Moffitt M. ASP-DAC 2008 (Proceedings of the 2008 Asia and South Pacific Design Automation Conference, Seoul, Korea, Jan 21-24, 2008) 226-231, 2008. Type: Proceedings
Routing is an essential step in the process of modern very large-scale integration (VLSI) physical design. Without an effective and efficient router, it is difficult to implement the physical layout of an integrated circuit that may co...
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Apr 17 2009 |
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The coming of age of (academic) global routing Moffitt M., Roy J., Markov I. Physical design (Proceedings of the 2008 International Symposium on Physical Design, Portland, Oregon, Apr 13-16, 2008) 148-155, 2008. Type: Proceedings
Very-large-scale integration (VLSI) combines thousands of transistor-based systems on a single chip. This paper is a concise and elegant repository of the current state of the art of VLSI global routing. The paper provides background i...
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Jun 12 2008 |
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Hierarchical partitioning of VLSI floorplans by staircases Majumder S., Sur-Kolay S., Bhattacharya B., Das S. ACM Transactions on Design Automation of Electronic Systems 12(1): 7-es, 2007. Type: Article
The partitioning of floorplans is an important topic in the field of very large-scale integration (VLSI) physical design automation. Proper partitioning of floorplans can lead to not only efficient insertion of repeaters, but also effi...
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Feb 6 2008 |
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A novel net-degree distribution model and its application to floorplanning benchmark generation Wan T., Chrzanowska-Jeske M. Integration, the VLSI Journal 40(4): 420-433, 2007. Type: Article
This paper provides an accurate estimate of interconnect net-degree distribution for multiterminal nets (referred to as a weighted exponential model), and for generating larger floorplanning benchmarks. The proposed technique is an int...
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Sep 26 2007 |
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An algorithm for integrated pin assignment and buffer planning Xiang H., Tang X., Wong M. ACM Transactions on Design Automation of Electronic Systems 10(3): 561-572, 2005. Type: Article
With a drastic reduction in minimum feature sizes, interconnects are dominating deep sub-micron very large-scale integration (VLSI) physical design. As such, several techniques have evolved to reduce the interconnect delay. One effecti...
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Nov 30 2005 |
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A differential equation for placement analysis Christie P. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9(6): 913-921, 2001. Type: Article
Most models for on-chip wire length estimation involve two tasks: the enumeration of two-terminal net placement sites, and the population of these sites using a function derived from Rent’s rule. Rent’s rule estimat...
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Jun 21 2002 |
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Optimal Placements of Flexible Objects: Part I: Analytical Results for the Unbounded Case Albrecht A., Cheung S., Hui K., Leung K., Wong C. IEEE Transactions on Computers 46(8): 890-904, 1997. Type: Article
These research papers consider the problem of placing two-dimensional deformable discs of equal size within a rigid boundary. Two cases are distinguished, depending on whether the disc is small compared with the overall area of the bou...
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Sep 1 1998 |
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Optimal Placements of Flexible Objects: Part II: A Simulated Annealing Approach for the Bounded Case Albrecht A., Cheung S., Hui K., Leung K., Wong C. IEEE Transactions on Computers 46(8): 905-929, 1997. Type: Article
These research papers consider the problem of placing two-dimensional deformable discs of equal size within a rigid boundary. Two cases are distinguished, depending on whether the disc is small compared with the overall area of the bou...
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Sep 1 1998 |
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Board-level multiterminal net routing for FPGA-based logic emulation Mak W., Wong D. ACM Transactions on Design Automation of Electronic Systems 2(2): 151-167, 1997. Type: Article
Field-programmable gate arrays (FPGAs) can be used effectively to emulate complex digital systems. This paper is concerned with their use in the emulation of complex digital designs. In a previous paper [1], the authors showed that the...
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Oct 1 1997 |
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Routing in a Three-Dimensional Chip Tong C., Wu C. IEEE Transactions on Computers 44(1): 106-117, 1995. Type: Article
A pseudo-three-dimensional routing for a chip with standard cells on multiple planes is presented. For each component plane of standard cells, the routing channel is defined between cell rows as conventional standard cell layout with t...
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Apr 1 1996 |
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