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Browse All Reviews > Hardware (B) > Logic Design (B.6) > Design Styles (B.6.1) > Cellular Arrays And Automata (B.6.1...)
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1-9 of 9
Reviews about "Cellular Arrays And Automata (B.6.1...)":
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Exercises in cellular automata and groups
Ceccherini-Silberstein T., Coornaert M., Springer International Publishing, Cham, Switzerland, 2023. 627 pp. Type: Book (9783031103902)
This book has been published as part of the “Springer Monographs in Mathematics” series. It complements the book Cellular automata and groups [1] and its forthcoming second edition by the same authors. The authors have also writ...
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Feb 6 2024 |
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Automatic cell placement for quantum-dot cellular automata
Ravichandran R., Lim S., Niemier M. Integration, the VLSI Journal 38(3): 541-548, 2005. Type: Article
Ravichandran, Lim, and Niemier develop the first cell-level placement of quantum-dot cellular automata (QCA) circuits to help automate the design process. QCA placement proceeds in three steps: zone partitioning, zone placement, and ce...
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Aug 17 2005 |
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Remarks on permutive cellular automata
Allouche J., Skordev G. Journal of Computer and System Sciences 67(1): 174-182, 2003. Type: Article
Cellular automata provide a fascinating, and often fun, technique for modeling complex, discrete, dynamic systems. Even relatively simple systems modeled using cellular automata can exhibit chaotic behavior. Therefore, significant inte...
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Dec 30 2003 |
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Place coding in analog VLSI
Landolt O., Kluwer Academic Publishers, Norwell, MA, 1998. Type: Book (9780792381945)
Intended for an audience of researchers and practicing hardware design engineers, this book describes a way of storing numbers in a digital circuit by encoding its value positionally into an array of circuits. The book is based on the ...
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Apr 1 1999 |
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On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement
Kim J., Reddy S. IEEE Transactions on Computers 38(4): 515-525, 1989. Type: Article
Existing methods for testing and reconfiguring systolic arrays assume fault-free alternate paths or registers and only address testing or easy reconfiguration of one processing element (PE) at a time. The authors describe algorithms th...
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Oct 1 1989 |
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Fault tolerant programming of a two-layer cellular array
Tóth N. Parallel processing by cellular automata and arrays (, Berlin, E. Germany, 1081987. Type: Proceedings
In this paper, a careful mathematical model is built to study the operation of two-dimensional meshes of nearest-neighbor connected processors. This model is then used to show that by replicating the array of processors (by having two ...
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Nov 1 1988 |
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Verification of a class of self-timed computational networks
Melhem R. BIT 27(4): 480-500, 1987. Type: Article
This paper stresses the importance of initial conditions for the correct operation of a network of processors. The author builds a general model of computation that has all reads of inputs followed by all computations followed by all o...
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Aug 1 1988 |
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Testing in two-dimensional iterative logic arrays
Cheng W., Patel J. Computers and Mathematics with Applications 13(5-6): 443-454, 1987. Type: Article
This paper deals with the problem of testing methods for iterative logic arrays (ILAs). ILAs implement general logic functions and contain identical cells and interconnections between cells. This structural regularity eases logic desig...
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Jul 1 1988 |
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Iterated interpolation using a systolic array
McKeown G. ACM Transactions on Mathematical Software 12(2): 162-170, 1986. Type: Article
This paper describes a systolic architecture for the implementation of Aitken’s method of iterated interpolation. Systolic architectures are composed by a number of identical and, usually, simple processors, connected in a su...
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Mar 1 1987 |
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