Computing Reviews
Today's Issue Hot Topics Search Browse Recommended My Account Log In
Home Topics Titles Quotes Blog Featured Help
Search
 
Paparao S Kavalipati

, California
 

Paparao Kavalipati is a software developer and consultant on electronics design automation (EDA) products with expertise in formal verification, logic synthesis, and related technologies. He is currently employed at Tabula Inc. Prior to that, he was a member of the R&D team at major EDA vendors like Mentor Graphics Corp. and Synopsys Inc.

With more than 18 years of experience in the industry, Paparao delivered new features and improvements for a range of products that include programmable logic devices, timing constraint verification, assertion synthesis, RTL compilation, model checking, equivalence checking, and simulation.

Paparao also offers development services and solutions to startup companies.  Working as an independent consultant, Paparao designed and developed a hybrid satisfiability engine for the verification of false paths and multi-cycle paths by formulating them as safety properties.

At Mentor Graphics, Paparao designed and implemented a high-level optimizer for assertion expressions, which benefited the 0in formal product in quickly verifying complex properties written in SVA and PSL. Paparao also contributed to the R&D efforts on low-power design verification, and synthesizing multi-clock SVA. At Synopsys, Paparao crafted various coding refinements to Magellan, Formality, and Scirocco products, covering a broad scope of projects on RTL synthesis, data path equivalence, and simulation speed-up.

His interests span a wide spectrum starting from fundamental algorithms, optimization methods, compilers, and automata theory as embedded in the art of electronics design and verification. Being an industrial researcher, he focuses on theoretical concepts that can relate well to pragmatic applications.

Attracted by the opportunities that Computing Reviews provides for continued learning, Paparao has been volunteering as a reviewer since 2008 and brings a practitioner’s point of view to the articles and books that he reads. He looks forward to keeping in touch with the technological and academic advances while rendering more reviews in the future.

Paparao received his master’s degree from the Indian Institute of Science, Bangalore, in 1996.


     

PIMap: a flexible framework for improving LUT-based technology mapping via parallelized iterative optimization
Liu G., Zhang Z.  ACM Transactions on Reconfigurable Technology and Systems 11(4): 1-23, 2019. Type: Article

Transforming gate-level Boolean logic into functionally equivalent lookup tables (LUTs) is a key step in the compilation of a design into field-programmable gate arrays (FPGAs). Tools typically deploy a sequence of logic optimizations, with an aim...

 

Cryptographic and information security approaches for images and videos
Ramakrishnan S.,  CRC Press, Inc., Boca Raton, FL, 2019. 986 pp. Type: Book (978-1-138563-84-1)

Cryptography is the art of securing communications transmitted through insecure channels. It consists of mechanisms to keep the data confidential by preventing access to unapproved individuals, maintaining the integrity of the data through an abil...

 

Applied machine learning
Forsyth D.,  Springer International Publishing, New York, NY, 2019. 494 pp. Type: Book (978-3-030181-13-0)

Machine learning methods find application in almost any domain that makes use of some form of computation. These algorithms build appropriate models that help in making predictions; thus, they are of interest in industry as well as in business sce...

 

A moderately exponential time algorithm for k-IBDD satisfiability
Nagao A., Seto K., Teruyama J.  Algorithmica 80(10): 2725-2741, 2018. Type: Article

Branching programs can be modeled using binary decision diagrams (BDDs), which are rooted directed acyclic graphs with vertices labeled using variables of the program, and two sink nodes representing zero and one. In an ordered BDD (OBDD), the ord...

 

Scatter search for minimizing weighted tardiness in a single machine scheduling with setups
González M., Palacios J., Vela C., Hernández-Arauzo A.  Journal of Heuristics 23(2-3): 81-110, 2017. Type: Article

Scatter search is a heuristic method of generating nonrandom solutions. It systematically explores the solution space by constructing new trial solutions from reference solutions using context knowledge. A standard template of the process consists...

 
  more...

 
Send Your Comments
Contact Us
Reproduction in whole or in part without permission is prohibited.   Copyright © 2000-2020 ThinkLoud, Inc.
Terms of Use
| Privacy Policy