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Paparao S Kavalipati
Tabula Inc.
Santa Clara, California
 

Paparao Kavalipati is a software developer and consultant on electronics design automation (EDA) products with expertise in formal verification, logic synthesis, and related technologies. He is currently employed at Tabula Inc. Prior to that, he was a member of the R&D team at major EDA vendors like Mentor Graphics Corp. and Synopsys Inc.

With more than 18 years of experience in the industry, Paparao delivered new features and improvements for a range of products that include programmable logic devices, timing constraint verification, assertion synthesis, RTL compilation, model checking, equivalence checking, and simulation.

Paparao also offers development services and solutions to startup companies.  Working as an independent consultant, Paparao designed and developed a hybrid satisfiability engine for the verification of false paths and multi-cycle paths by formulating them as safety properties.

At Mentor Graphics, Paparao designed and implemented a high-level optimizer for assertion expressions, which benefited the 0in formal product in quickly verifying complex properties written in SVA and PSL. Paparao also contributed to the R&D efforts on low-power design verification, and synthesizing multi-clock SVA. At Synopsys, Paparao crafted various coding refinements to Magellan, Formality, and Scirocco products, covering a broad scope of projects on RTL synthesis, data path equivalence, and simulation speed-up.

His interests span a wide spectrum starting from fundamental algorithms, optimization methods, compilers, and automata theory as embedded in the art of electronics design and verification. Being an industrial researcher, he focuses on theoretical concepts that can relate well to pragmatic applications.

Attracted by the opportunities that Computing Reviews provides for continued learning, Paparao has been volunteering as a reviewer since 2008 and brings a practitioner’s point of view to the articles and books that he reads. He looks forward to keeping in touch with the technological and academic advances while rendering more reviews in the future.

Paparao received his master’s degree from the Indian Institute of Science, Bangalore, in 1996.


     

High-performance implementation of regular and easily scalable sorting networks on an FPGA
Sklyarov V., Skliarova I.  Microprocessors & Microsystems 38(5): 470-484, 2014. Type: Article

Sorting networks are hardware sorter circuits consisting of comparators. Each comparator takes two input numbers and produces the maximum and minimum of those numbers at its outputs. Since the comparisons run in parallel, such networks are...

 

 The Merino-Welsh conjecture holds for series-parallel graphs
Noble S., Royle G.  European Journal of Combinatorics 3824-35, 2014. Type: Article

Orientation is an assignment of direction to each edge of an undirected graph. When none of the directed edges is in a cycle, the orientation is called acyclic. When every directed edge is in some cycle, the orientation is called totally...

 

Data structures resilient to memory faults: an experimental study of dictionaries
Ferraro-Petrillo U., Grandoni F., Italiano G.  Journal of Experimental Algorithmics 181.1-1.14, 2013. Type: Article

Soft errors in electronics equipment can be caused by alpha particles or noise, and can change data that is being processed. The chance of these errors occuring increases with the size and speed of the memory used by the component. Memory cells...

 

The hardness of counting full words compatible with partial words
Manea F., Tiseanu C.  Journal of Computer and System Sciences 79(1): 7-22, 2013. Type: Article

Sequences of symbols from a given alphabet are known as words. If symbols are unknown at some positions, then such sequences are known as partial words. Two partial words are said to be compatible when they agree in all positions where they are...

 

Finite state machines in hardware: theory and design (with VHDL and SystemVerilog)
Pedroni V.,  The MIT Press, Cambridge, MA, 2013. 352 pp. Type: Book (978-0-262019-66-8)

Digital circuits where the output values depend on the state of the system are called sequential. A finite state machine (FSM) is a modeling technique for sequential circuits. At any point of its operation, the machine will be in one of a finite...

 
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