The authors present a novel cogurable accelerator engine for matrix operations (CAEMO) for improving computational performance on matrix- or block-based algorithms. Because many applications are based on the relationships between data neighbors, adjacency, connectivity, regions and boundaries, and block dataload and storage, such as image/video processing and the advanced encryption standard (AES), the proposed work has great potential to increase the energy efficiency of such data processing.

The platform is extendable and scalable to implement future complex operations on a matrix, and the interface is designed with the widely used advanced microcontroller bus architecture (AMBA) advanced extensible interface (AXI) standard. To integrate the whole system on a chip (SoC) (CAEMO plus AXI plus data memory access (DMA)), the coprocessor’s hardware overhead is sort of large, particularly for the use of inputs/outputs (IOs) and lookup tables (LUTs).

The tradeoff or balance between design and energy savings due to the high-efficiency scheduler should be estimated in future work. Current chip architectures only support linear data transfers, either burst or wrap types. The proposed work on matrix-based implementations could improve memory access performance. By integrating the coprocessor with the traditional SoC architecture, this work may achieve greater energy efficiency for specific block transfer operations on many image processing and machine learning algorithms, for example, applications with frequent matrix-based computations.