Computing Reviews

Frame buffer-less stream processor for accurate real-time interest point detection
Licciardo G., Boesch T., Pau D., Di Benedetto L. Integration, the VLSI Journal54(C):10-23,2016.Type:Article
Date Reviewed: 11/16/16

In the big data era, pictures are used as key information points in various applications such as ecommerce, entertainment, social networking, and medical diagnostics. Images contain huge amounts of information, and processing an image requires many computational resources. Image retrieval, a solution for extracting key features of images, has received much attention in recent years. Many researchers have proposed novel software solutions, like novel algorithms, and hardware solutions, like hardware accelerators, to speed up computation while keeping costs low. For example, most of the hardware solutions trade accuracy for additional area and power. Many proposed strategies explore the parallelism of the computation, but with a higher hardware cost.

This paper lies in the scope of hardware solutions: it proposes a novel accelerator that is able to overcome previous limitations. An application-specific processor is proposed to detect the interest point and refine it based on the difference-of-Gaussian calculation and scale-invariant feature transform (SIFT) refinement methods. The novelty of this work is that it takes all of the best state-of-the-art approaches and creates a scale-space pyramid for extraction and refinement. In this way, hardware resources and computation time are significantly improved. To evaluate the effectiveness of the proposed design, both field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms are used. On the FPGA platform, it can achieve a maximum frequency of 309MHz; on the ASIC platform, it can achieve a maximum frequency of 1.2GHz in a 28 FDSOI technology.

This work contains a very comprehensive analysis, from theoretical to experimental evaluations. It provides a very good example of evaluating a novel accelerator design. By mapping it to both FPGA and ASIC platforms, it gives readers a very clear vision of using this architecture in various applications and platforms. Overall, this paper proposes a very interesting design and the evaluation is well presented.

Reviewer:  Xinfei Guo Review #: CR144927 (1703-0182)

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