The design of modern integrated circuits has become so complex that it is no longer possible to imagine a tool flow that doesn’t start from a specification in a higher-level hardware description language (HDL). Among the available choices, Verilog has proven to be the most popular language for this purpose. Obviously, users writing such an abstract model need a way to check its correctness, and many simulators are available that support the desired feature set.

The authors here have set out with an ambitious goal to provide a survey of the simulator technology, as the title of this paper advertises. However, the material and contents that they have produced fall short of those high expectations.

The paper starts with an introductory presentation through the first three sections, before getting to some discussion of the various types of simulators in sections 4 and 5. Then, the authors recollect performance benchmarks published elsewhere to compare the various simulators in section 6, before making closing comments in the last two sections.

Overall, the information and insight delivered are elementary and lack technical rigor. Several expected items are missing and should have been mentioned since this is a survey paper. At least a brief description of the scheduling semantics needs to be included. Also, the authors have ignored cycle-based simulation technology altogether. Though commercial tools are listed, open-source efforts in developing Verilog simulators are not mentioned. Internals of the simulator algorithms and implementation details are not covered.

Verilog simulation is a central piece of chip verification, and it is a challenge to capture the essence of its entire breadth and influence in a short paper. The authors have made an attempt at the task, but could have organized it better.