The problem of “useless instruction execution” is addressed in this paper. An instruction is useless if the result is never used. With reasonable compilers, this problem can only take place when conditional branches occur between the instruction and the use. The paper proposes a new variation on hardware scheduling for a superscalar processor that delays the execution of the instruction until the value is about to be used. The instruction is considered useless and is discarded if the register holding the value is changed before any use.

The scheduling algorithm tracks the speculative execution of the conditional branches that occur following the instruction. It differentiates between speculative and deterministic execution of an instruction. When a nonspeculative use of the instruction result occurs, the instruction is executed.

Mahjur, Taghizadeh, and Jahangir make the argument that the scheduling algorithm will slow the execution by at most one instruction time. When useless instructions are executed, it will speed up execution because the execution units will not have to deal with the useless instructions. They argue that the implementation costs for memory and hardware are small.

This is an attractive hardware algorithm; however, it does cause difficulty for optimizing compilers. Compilers insert load operations to ensure that the data cache contains data before it is needed. This is done by inserting load operations early in the execution of the algorithm, so the data will be in place when used. This algorithm will eliminate or delay these instructions until the data is used. In either case, the cache does not contain the data early enough. The hardware must contain some form of load instruction or cache manipulation instruction that will always be useful.