Vassiliadis et al. discuss a new design paradigm that combines a general-purpose processor with a reconfigurable custom processor in a single integrated system suitable for implementation on programmable devices, such as field programmable gate array (FPGA) components. A general-purpose processor is modified by adding at most eight new instruction codes, and a small set of exchange registers that are used to pass parameters from the general-purpose processor to the reconfigurable custom processor, and results computed by the reconfigurable custom processor back to the general-purpose processor. The reconfigurable custom processor has its own specialized microcode control unit. A synthesizable arbiter decides whether an instruction is passed to the general-purpose processor or to the reconfigurable custom processor.

The authors extend an existing compiler to incorporate the reconfigurable processor instructions and the exchange registers. Support for parallel operation is claimed, but is not demonstrated in the examples in the paper.

I see great potential for this type of architecture. The paper will be of interest to a wide audience, including those involved in architecture design, reconfigurable custom computing design, and FPGA design. The paper is well written, and easily understandable for a general audience. Enough details are included to interest specialists as well.