The synthesis system to design finite-state machines described here allows the designer to explore a variety of implementations that differ in their speed of operation. The designer does this by specifying the number of levels of logic in the design.

To an experienced logic designer the ideas in the paper may be well-known, but the paper exposes readers to the details of the synthesis procedure used to implement finite state machines. It does not assume much prior knowledge about logic synthesis, and it explains the core ideas well.

From a technical viewpoint, a possible shortcoming is the assumption that the speed of the circuit is related strongly to the number of levels of logic. Restricting the number of levels of logic is not, by itself, sufficient to guarantee a faster circuit. The technology mapping phase is crucial in determining the speed of the final implementation. In addition, the multilevel minimization techniques that the authors use can (and in the example provided do) increase the number of levels of logic.

The division of the design process into a technology-independent phase (factorization and multilevel minimization) and a technology mapping phase is very useful. It allows different technologies to be explored without having to redo the entire synthesis process.

Overall, the paper provides a good overview of a synthesis procedure for finite state machines. It presents a method of exploring the design space so as to develop an implementation that meets the desired speed constraints.