Computing Reviews
Today's Issue Hot Topics Search Browse Recommended My Account Log In
Review Help
Efficient instruction scheduling using real-time load delay tracking
Diavastos A., Carlson T. ACM Transactions on Computer Systems40 (1-4):1-21,2022.Type:Article
Date Reviewed: Oct 27 2023

Central processing unit (CPU) architectures with out-of-order instruction scheduling use, among other data, static instruction-timing information to create good schedules. The work reported in this paper describes the result of augmenting out-of-order instruction scheduling with dynamic timing information derived during execution. Simulations show the new architecture demonstrates a favorable balance between performance loss resulting from more-constrained schedules and the simpler and more power-efficient scheduling mechanisms.

Dynamic instruction-timing information is captured for load instructions within loop iterations; other instructions are scheduled with static timing information. Instruction issue is done via priority queue ordered by expected ready time. The simplicity of the mechanisms implementing these functions provides the benefit; for example, complex resource-scheduling schemes can be replaced by assigning queues to resources. The cost comes from, among other sources, inaccuracies in applying intra-iteration timing information across iterations; experiments with Standard Performance Evaluation Corporation (SPEC) benchmarks show timing information has roughly 90 percent consistency between successive iterations.

Simulations show the results of incorporating dynamic timing information in out-of-order instruction scheduling. When compared to baseline out-of-order schedules, schedules using dynamic timings show a roughly 13 percent drop-off in performance. On the other side, power consumption drops by roughly 20 percent, and chip area is reduced by roughly 15 percent. More detailed simulations pick apart the various components on both sides of the tradeoff.

The writing is clear, and the details are laid out effectively. The numbers, however, are a little difficult to trace through the explanations, although the general points come through. The bibliography is fine, although for some reason there are no references to scheduling algorithms for drum memory.

Reviewer:  R. Clayton Review #: CR147658
Bookmark and Share
Scheduling (D.4.1 ... )
Data-Flow Architectures (C.1.3 ... )
Data-Flow Languages (D.3.2 ... )
Would you recommend this review?
Other reviews under "Scheduling": Date
The gradient model load balancing method
Lin F., Keller R. (ed) IEEE Transactions on Software Engineering 13(1): 32-38, 1987. Type: Article
Sep 1 1987
Preemptive scheduling of a multiprocessor system with memories to minimize maximum lateness
Lai T., Sahni S. SIAM Journal on Computing 13(4): 690-704, 1984. Type: Article
Jul 1 1985
Scheduling independent tasks on uniform processors
Dobson G. SIAM Journal on Computing 13(4): 705-716, 1984. Type: Article
Apr 1 1986

E-Mail This Printer-Friendly
Send Your Comments
Contact Us
Reproduction in whole or in part without permission is prohibited.   Copyright 1999-2023 ThinkLoud®
Terms of Use
| Privacy Policy