During the processes of designing and manufacturing integrated circuits, the yield, which is calculated as the percentage of manufactured integrated circuits that pass all of the tests and function properly, is one of the major concerns. An integrated circuit design with relatively high yield not only indicates that its chip supplier and semiconductor foundry can have relatively high profit margins, but also implies that the manufactured chips will be relatively reliable. To improve the yield of integrated circuits, semiconductor foundries have released design kits that contain design for manufacturability (DFM) rules so that circuit designers can apply these rules to their designs.

DFM rules for a specific process node are a set of constraints that can be placed on physical layouts of integrated circuit designs in the hope of improving the yield of these designs. Examples of DFM rules include width rules, which specify minimum widths for layout shapes on specific layers, and spacing rules, which specify minimum spacing distances between layout shapes on specific layers. Although a DFM rule can look similar to a design rule checking (DRC) rule, a DFM rule is different from a relevant DRC rule at a process node in that a DFM rule restricts designs to meet more stringent constraints than a relevant DRC rule does. Additionally, DFM rules can include process hotspot patterns. To check whether or not a layout design violates DFM rules, relevant electronic design automation (EDA) software tools have been developed and widely used in the semiconductor industry.

A DFM rule can be an optional rule, meaning that circuit designers are free to decide whether or not to allow layouts to violate the rule. Since making layouts conform to all DFM rules can come with the penalties of additional die area and power, there exists the need to know the impact of a DFM rule on yield if a design violates the rule. Thus, the paper proposes a methodology called DREAMS (short for “design for manufacturability rule evaluation using manufactured silicon”) in order to evaluate the importance of each DFM rule. As a result, designers can make use of the information and impose only critical DFM rules, instead of all DFM rules, on their layout designs.

The methodology presented in the paper uses the information from the results of executing a DFM rule deck on the physical layout of a circuit design, as well as the results of logic diagnosis performed on failed integrated circuits (ICs) of the design. Note that failed ICs are fabricated chips that do not function properly. In the proposed methodology, moreover, techniques that are used include rule-candidate correlation, an expectation-maximization (EM) based algorithm, confidence interval estimation, and diagnostic resolution improvement. Experimental results show that, in terms of identifying critical DFM rules, the proposed methodology is more reliable than methodologies published previously. Finally, the methodology is pragmatic since the paper has demonstrated that it has been applied in an industrial environment.