Because of the programmability challenge of timing-based hardware description languages (HDL) involving Verilog and VHDL, today many higher-level design languages and tools have been presented in academy and industry, in order to construct a digital system above the register-transfer level (RTL). To the best of my knowledge, these technologies were partially adopted in the field-programmable gate array (FPGA) design field; however, application-specific integrated circuit (ASIC) design is still dependent on RTL description due to the complex timing issues and high-performance requirement of ASICs.

This paper presents a novel integrated circuit (IC) design tool capable of generating HDL code and testbench at a higher abstract level, as well as evaluating the system performance. The tool is developed using Simulink and executable micro-architectural specification (xMAS) language. The design flow and benchmark are thoroughly introduced. Indeed, the design flow can be improved a lot by employing the algorithm-level technology. Since the timing check is one of the most important steps of the back-end procedure, which is likely to affect the functions and tape-out of a chip, the architectural-level design can reduce risk and time-to-market without static timing analysis pre- and post-simulation.

However, my main concern is the scalability of the proposed method. The contribution is likely limited to a narrow range of projects, maybe just for some simulation-based projects and performance estimation systems.