There are occasions when a delay of several clock cycles is required for a serial data stream. If the “density” of transitions is low, meaning the probability of transitions with respect to the clock is small, and the delay time required is long, the two standard approaches are inefficient. A classical lengthy shift register can requires much hardware and consumes power and clock resources. As an alternative, a memory-based approach can require large memory allocations where not much actual data is stored.

The technique suggested is a straightforward device. Only store the transitions and the times they occur. Combined with the delay, when the delay expires for each transition, make the output correspond to the original input. Of course, there are added complexities. An actual implementation must consider the width of the expected input signal; a delay that is too short or long would reduce the efficiency of the device.

Section 3 discusses the completed logic description of the programmable delay circuit, and covers various error conditions. Sections 4 and 5 provide a mathematical basis for the logic and power improvements. Section 6 gives rules for implementation with several example bit widths and how many transitions should be accommodated. Section 7 describes an implementation and its performance. A video example is presented in section 8, where the suggested circuit requires 547 flip-flops; a standard shift register would have required 15,780 FF.