Computing Reviews
Today's Issue Hot Topics Search Browse Recommended My Account Log In
Review Help
Search
Frame buffer-less stream processor for accurate real-time interest point detection
Licciardo G., Boesch T., Pau D., Di Benedetto L. Integration, the VLSI Journal54 (C):10-23,2016.Type:Article
Date Reviewed: Nov 16 2016

In the big data era, pictures are used as key information points in various applications such as ecommerce, entertainment, social networking, and medical diagnostics. Images contain huge amounts of information, and processing an image requires many computational resources. Image retrieval, a solution for extracting key features of images, has received much attention in recent years. Many researchers have proposed novel software solutions, like novel algorithms, and hardware solutions, like hardware accelerators, to speed up computation while keeping costs low. For example, most of the hardware solutions trade accuracy for additional area and power. Many proposed strategies explore the parallelism of the computation, but with a higher hardware cost.

This paper lies in the scope of hardware solutions: it proposes a novel accelerator that is able to overcome previous limitations. An application-specific processor is proposed to detect the interest point and refine it based on the difference-of-Gaussian calculation and scale-invariant feature transform (SIFT) refinement methods. The novelty of this work is that it takes all of the best state-of-the-art approaches and creates a scale-space pyramid for extraction and refinement. In this way, hardware resources and computation time are significantly improved. To evaluate the effectiveness of the proposed design, both field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms are used. On the FPGA platform, it can achieve a maximum frequency of 309MHz; on the ASIC platform, it can achieve a maximum frequency of 1.2GHz in a 28 FDSOI technology.

This work contains a very comprehensive analysis, from theoretical to experimental evaluations. It provides a very good example of evaluating a novel accelerator design. By mapping it to both FPGA and ASIC platforms, it gives readers a very clear vision of using this architecture in various applications and platforms. Overall, this paper proposes a very interesting design and the evaluation is well presented.

Reviewer:  Xinfei Guo Review #: CR144927 (1703-0182)
Bookmark and Share
  Featured Reviewer  
 
VLSI (Very Large Scale Integration) (B.7.1 ... )
 
Would you recommend this review?
yes
no
Other reviews under "VLSI (Very Large Scale Integration)": Date
Area-time optimal VLSI integer multiplier with minimum computation time
Mehlhorn K., Preparata F. Information and Control 58(1-3): 137-156, 1984. Type: Article
Jun 1 1985
A rapid turnaround design of a high speed VLSI search processor
Matoba T., Lee K., Herman G., W. H. J. Integration, the VLSI Journal 10(3): 319-337, 1991. Type: Article
Mar 1 1992
An efficient heuristic for standard-cell placement
Kappen H. Integration, the VLSI Journal 10(3): 251-269, 1991. Type: Article
Jul 1 1992
more...

E-Mail This Printer-Friendly
Send Your Comments
Contact Us
Reproduction in whole or in part without permission is prohibited.   Copyright 1999-2024 ThinkLoud®
Terms of Use
| Privacy Policy