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RT level timing modeling for aging prediction
Koppaetzky N., Metzdorf M., Eilers R., Helms D., Nebel W.  DATE 2016 (Proceedings of the 2016 Conference on Design, Automation & Test in Europe, Dresden, Germany, Mar 14-18, 2016)297-300.2016.Type:Proceedings
Date Reviewed: Sep 9 2016

Transistor aging has grown as a critical reliability issue that shortens the lifetime of electronic devices and slows down the circuits inside these devices. During the past decade, researchers have proposed various techniques to deal with aging-related issues. One of the most effective ways of coping with aging is to consider it during the design phase, when the circuit designers estimate the potential aging-induced performance degradation and lifetime before they design the circuit. Estimating aging at the circuit level is challenging due to the following reasons. First, aging is a relatively new phenomenon: the mechanism behind it is still somewhat debatable, so even at the physics level it is still not quite clear; there is no one standard equation or model that can be used to characterize aging accurately. Second, aging-related information hasn’t been included in the portable design kit (PDK) yet, and this makes it really hard to do circuit-level simulation, which can carry aging information. This paper attempts to solve this issue by proposing ways of doing register-transfer-level (RTL) aging simulations.

The paper’s key idea is to convert aging-induced threshold voltage shifts to the sum of the gate delay of the basic inverter, and then several coefficients are included to fit the data. To get these coefficients, the input signal probabilities, temperature, and voltage profile need to be given. With the help of the static timing analysis, these coefficients are decided. This paper presents some early results, which show the flow works well and can predict the performance degradation resulting from aging.

Reviewer:  Xinfei Guo Review #: CR144752 (1612-0888)
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