This paper deals with the problem of efficiently mapping programs to an accelerator that presents runtime choices about how to map programs to computation elements either because the accelerator configuration is unknown at compile time or because of configuration changes brought on by failure.

The solution proposed in the paper is to require programs to be expressed as a static dataflow graph with compute nodes corresponding to functions and edges representing communication of data from producing functions to consuming ones. Edges are annotated with “sample rates”: two numbers that specify constraints on how fast results can be produced and how fast they can be consumed by compute units. The runtime problem then becomes: assign compute cores to nodes in the dataflow graph to maximize overall throughput while respecting the sample rates allowed at consuming cores. Although the optimal solution would require exponential time, a heuristic that greedily maximizes the increment in throughput for every core to be assigned in order seems to work well.

Overall, this interesting read with a practical evaluation based on Intel Xeon Phis suggests that this technique might be useful in practice. It is unclear how easy it would be to assign sample rates to a dataflow graph as required in the paper; assuming this were possible, the scheduling algorithm in the paper clearly merits consideration.