Hardware accelerators have seen increasing use in the last decade and can provide significant performance benefits compared to traditional central processing unit (CPU) architectures, especially for massively parallel applications. Specific architectures such as graphics processing units (GPUs) and field programmable gate arrays (FPGAs) have been successfully used to accelerate a variety of applications, but usually in homogeneous environments with only one type of accelerator architecture present in a system. The use of multiple accelerator architectures in a system for a single application is a recent phenomenon.
Thoma et al. focus on an important aspect of accelerators that are currently being used: communication over the peripheral component interconnect express (PCIe) bus. The PCIe bus connects the CPU to the accelerator, and the accelerators to each other. The authors’ specific contribution is an open-source implementation of direct FPGA-GPU communication via PCIe. Using the FPGA as a direct memory access (DMA) master, bandwidth experiments are performed using real equipment. One strange aspect of the experimental setup is that the GPU used is four generations old (released in 2007), and no explanation as to why that model was tested is given. The results of the experiments are more troubling; read operations are two orders of magnitude slower than write operations. While the authors acknowledge this, they are unable to provide any explanation as to why this is true.
It is likely true that the use of multiple accelerators of different architectures will become more common in future research applications. For these types of environments, cross communication will be critically important to performance. This work presents a step in the direction to optimize data transfers over the PCIe bus. While it does not seem ready for production use, one can hope that future generations of this technology will enable rapid development of applications that rely on high-speed data transfers between heterogeneous accelerator architectures.
