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Delay/power modeling and optimization of FinFET circuit modules under PVT variations: observing the trends between the 22nm and 14nm technology nodes
Tang A., Gao X., Chen L., Jha N. ACM Journal on Emerging Technologies in Computing Systems12 (4):1-21,2016.Type:Article
Date Reviewed: Apr 28 2016

Driven by the increasing demands of low power and high performance, the semiconductor industry has pushed the device down to below 20 nanometer (nm) scale. Downscaling introduced several challenges, among which short channel effect is one of the most critical ones. The direct impact for short channel effect is that it is very hard to turn off the transistor, which means the undesired leakage current will be large. The industry introduced FinFET, a tri-gate 3D transistor that has a very good ability to mitigate short channel effect while satisfying the device-shrinking requirement for extending Moore’s law. Due to the physical differences between FinFET and planar devices, the new modeling and design methodology need to be adjusted based on the uniqueness of FinFET devices, such as the effects of process, voltage, and temperature (PVT) variations that are induced during fabrication and operations. Also, other research questions include how these device- and circuit-level features affect the architecture-level design, and how these features can improve the architecture-level metrics.

In this paper, Tang et al. address the above questions by proposing a delay and power modeling framework for analyzing FinFET logic circuits under PVT variations; the circuit-level model is plugged into the architecture-level simulators to evaluate the overall impact at a higher level. The flow is detailed in the paper. For example, at the device level, the TCAD tool is used for obtaining the FinFET device-level parameters that can be used in the circuit-level simulations. PVT variations are introduced as a statistical distribution. At the architecture level, both cache and functional unit (FU) are used as the evaluation platform. A performance/power modeling framework McPAT is used as the architecture-level simulator, which works together with the Synopsys design compiler and a genetic algorithm called GenFin. Overall, the modeling framework takes care of the FinFET device-level characteristics and transforms these impacts to the higher level while considering the PVT variations. As for the results, the paper compares the power and performance between the 14 nm and 22 nm nodes. The modeling framework captures the impact of PVT variations statistically (error is below 3.3 percent).

The proposed modeling framework is robust and can assist the circuit designers and computer architects to optimize power and performance metrics for FinFET design. The flow can even be adapted to other technologies for doing similar analysis. The simulated results also show that 14 nm FinFET has a wide range of variability, and this indicates that the PVT variations in FinFET design need to be addressed in a very early design stage and in a systematic way so that the overall design is robust.

Reviewer:  Xinfei Guo Review #: CR144364 (1607-0500)
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