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Improving write performance by controlling target resistance distributions in MLC PRAM
Kim Y., Yoo S., Lee S. ACM Transactions on Design Automation of Electronic Systems21 (2):1-27,2016.Type:Article
Date Reviewed: Apr 19 2016

Memory technology is important to everyone who wants his computer to be faster. Dynamic random-access memory (DRAM) has been used as the main memory technology for decades, but it has some overhead related to its cost and power consumption. Research in this domain continues to find alternative solutions that provide the same or better performance, but with lower cost and lower power consumption. Phase-change RAM (PRAM) technology is one of these alternatives, but has poor write performance. This paper proposes two techniques to improve the write performance of the hybrid PRAM/DRAM system. First, multiple RESET/SET operations are proposed to reduce the latency for intermediate logic levels. Also, a two-step write scheme is adopted to perform a first lightweight write that has short retention time; then, during idle time, the lifetime of this data under lightweight write is increased by performing a completion write.

This paper will be interesting to computer scientists who are developing high-scale scientific applications in different domains such as biology, physics, chemistry, medicine, and so on, and need to know about the current research and future directions with regard to memory technology. This will make it possible to tune algorithms to make the best use of memory.

Reviewer:  Dounia Khaldi Review #: CR144328 (1607-0498)
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Semiconductor Memories (B.3.1 )
 
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A SISO register circuit tailored for input data with low transition probability
Napoli E., Castellano G., De Caro D., Esposito D., Petra N., Strollo A. IEEE Transactions on Computers 66(1): 45-51, 2017. Type: Article
May 31 2017

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