Modern networks on chip (NoC)-based processors often integrate tens of functional components connected by an on-chip network. The behavior of the network is an important component of overall system performance. A metric that can be derived analytically that is also a good characterization of how the NoC will behave under load is therefore extremely useful.

This paper proposes using the average latency under zero load as such a metric. This is simply the average distance traversed by a packet given the traffic matrix (relative amount of flows between pairs of nodes) and assuming no congestion. The authors demonstrate the surprising result that this simple static metric is a high-fidelity predictor of performance under load even with deflection NoCs (where adaptive routing is a function of load). They define high fidelity as network A having lower latency than network B when network A can be analytically shown to have lower average latency under zero load than network B. This is clearly a very useful result for a system design concerned with hotspots and placement decisions with NoCs. The authors validate this hypothesis through cycle accurate simulation of a number of topologies and temporal distributions (random traffic generation as a function of time).

This paper is an excellent read for practitioners in the NoC area and provides a valuable metric for systems design in this space.