A cycle-accurate simulation environment for evaluating the topologies aiming to reduce insertion loss in photonic networks is introduced in this paper. The paper considers the D-Mesh topology, which is designed based on space routing in on-chip photonic networks; these networks aim to achieve a lower network diameter and a lower number of waveguide crossings. D-Mesh could serve to decrease insertion loss and to increase network scalability by allowing more wavelength channels.

Overall, the results presented in this paper are not very informative when it comes to evaluating the validity of the design of the D-Mesh topology. Even though the results look good, the whole design is straightforward and doesn’t seem novel because of the usage of multiple wavelength channels. This leads me to wonder: What is the significant novelty in the design of D-Mesh topology?