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Customized pipeline and instruction set architecture for embedded processing engines
Yazdanbakhsh A., Salehi M., Fakhraie S. The Journal of Supercomputing68 (2):948-977,2014.Type:Article
Date Reviewed: Apr 9 2015

This research aims to improve performance in embedded application domains. The authors have not proposed an entirely new set of instructions, but rather have customized instructions by building a dataflow graph (DFG) and profiling the application that is to be executed. In addition, they obtain various statistics from the applications, such as iteration frequency, basic blocks required, and dynamic execution blocks. Thus, by obtaining software latency from the code, they try to identify the hardware latency by the number of cycles. The number of basic inputs/outputs is identified from read/write operations from each block. If the number of inputs/outputs exceeds the available read/write ports of the register file that is available, then the pipelining method is used to improve the performance. With this method of performing multi-cycle read/write operations in order to stay within the register file limit, some performance loss happens. However, the method also helps to increase the bandwidth of the register file.

As a result of applying the customized processor to meet the analyzed goal with the long clock cycle, performance improves by about five percent and the control complexity increases. However, this particular research focuses on single-issue in-order execution, which exploits “backward” logic to resolve data hazards that can arise from pipelining. The proposed architecture also tries to increase the number of read and write ports as the demand rises for more input and output. The base instruction size is a 32-bit microprocessor with MIPS architecture. It is used differently to address the customized need of the applications that are analyzed before being executed. As a result, by observing the graph, the performance improvement of the customized instruction is about ten percent.

There are several issues the authors have not taken into consideration. First of all, even in the current embedded systems, the trend is to switch to a multicore processor rather than a single processor system. Second, the present architectures use complex out-of-order execution and forwarding to avoid different hazards. The proposed architecture is very limited in addressing various issues that are relevant to the current processors in embedded systems available on the market. A strength of this method is that it obtains the information from the profiler to adjust the register file according to need and attempts to increase the bandwidth. When we consider a new architecture, we need to look at it from different aspects to obtain overall performance rather than just solving the register file usage issue. Finally, the research tries to address a very limited concern of the architecture: the efficient use of the register read/write port. The authors must consider the current complex embedded processors available on the market rather than considering a simple MIPS-like single processor and doing something to improve its performance.

Reviewer:  J. Arul Review #: CR143327 (1507-0583)
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