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RIVER: reconfigurable flow and fabric for real-time signal processing on FPGAs
Brugger C., Hillenbrand D., Balzer M. ACM Transactions on Reconfigurable Technology and Systems7 (3):1-16,2014.Type:Article
Date Reviewed: Dec 11 2014

The authors of this paper describe an architecture called RIVER and a design flow for field-programmable gate arrays (FPGAs). They have built a precompiled library consisting of many combinations and permutations of basic “building blocks that provide storage, dataflow, computation, and control,” and have used two kernels, one from signal processing and another from financial modeling, to evaluate their tool.

The authors attract attention with a claim in the introduction that they “are the first to propose online design space exploration based on repositories of precompiled cores assembled of common building blocks.” However, they do not do a good job explaining what exactly they mean by “online.”

I like the basic building blocks of the architecture. They seem to support streaming signal processing kernels very well.

The design flow is poorly explained. My understanding is that there are two parts: one where thousands of designs are synthesized using a cloud-based synthesis framework and copied into a library, and one where the user maps his or her application using one of the precompiled bit files into the FPGA. The authors need to do a better job explaining the latter part.

The flow seems restrictive. First, it doesn’t allow for the insertion of custom Internet protocol (IP) addresses, which may be required for certain applications. Second, it’s a domain-specific architecture that only supports applications that can be described entirely using the basic building blocks. This is not necessarily a negative thing because signal processing applications, which the paper suggests are supported, form a big chunk of the FPGA market segment.

The paper would definitely benefit from an elaborated evaluation of several applications, possibly with different characteristics. Also, there are several grammatical mistakes.

Reviewer:  Sunil Shukla Review #: CR143001 (1504-0292)
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Real-Time And Embedded Systems (C.3 ... )
 
 
Data-Flow Architectures (C.1.3 ... )
 
 
Domain-Specific Architectures (D.2.11 ... )
 
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