Higher voltages improve transistor switching times, but the speed achievable at a fixed voltage degrades with use. That degradation is also temperature specific. This means that a new multicore central processing unit (CPU) will have to either run hotter or run slower as it gets older. The relationships between these factors are nonlinear, and it is this nonlinearity that the authors exploit in this paper.

Although all cores will start off being homogeneous, over time some will degrade faster than others. By mounting sensors for both temperature and the aging effect of negative-bias temperature instability inside the silicon, the core scheduler can be made aware of both the thermal headroom available at each core and the voltage level that will be required for a given clock frequency. Given all this extra information, the authors propose to give the jobs on the critical path to the most competitive cores of a CPU, rather than distributing the workload comprising a task evenly across all the cores. The jobs not on the critical path can then be executed at a slower pace by slowing down the cores.

The authors use simulation to show that their proposed scheme reduces both power consumption and the mean time to failure. These benefits do come at the cost of higher complexity, however. Not only does the design require extra silicon to build the sensors into the cores, but, because all the cores run at different clock frequencies, it also requires the efficient handling of the asynchronous inter-core communication.