By selectively replicating only those instructions that have the highest probability of failing due to soft errors--caused by particle strikes, noise, electromagnetic interference, or electrostatic discharge--Vera et al. are able to reduce the failures in time (FIT) (number of errors in one billion device-hours of operation) by 65 percent, with less than four percent performance degradation and with one percent hardware overhead.

Compared with the 100 percent reduction when using a competing method with performance degradation of 32 percent, the proposed technique provides a possible trade-off in situations involving noncritical applications, where infrequent errors are acceptable.

The techniques employed are only applicable to the specific processor used in the study, but the principles, which are fairly self-evident, are likely to apply to other processors. The paper is also valuable as a tutorial in soft errors, including appropriate analysis techniques.

In summary, Vera et al. validate an intuitively obvious anecdotal claim with real numbers, on a real processor.