Sekar et al. present FLEXBUS, a novel on-chip communication bus topology that can be configured to map components in a system-on-chip (SoC) design based on application traffic characteristics.

FLEXBUS is targeted toward runtime reconfiguration by using a dynamic bridge bypass technique. This technique allows runtime fusing and splitting of bus segments, along with component remapping based on traffic characteristics. FLEXBUS is applied to two SoC designs: an IEEE 802.11 media access control (MAC) processor and a universal mobile telecommunications system (UMTS) Turbo decoder. FLEXBUS is evaluated with respect to the total chip overhead and the delay penalty incurred, compared to statically configured architectures.

Overall, the paper is ideal for users researching on-chip communication architectures targeted toward input/output bound problems.