Over the past decades, on-chip integration has been one of the major forces behind the performance improvements in electronic and computing systems. First, memory and application-specific accelerators made their way into processor chips, improving performance by reducing the latency of the communication with the main central processing unit (CPU). Then, multiple processing cores were integrated on a single chip, so that the potential parallelism they introduced could compensate for the plateau in clock frequency that is due to silicon technology limitations. State-of-the-art chips already integrate dozens of processing cores and complex memory hierarchies; many embedded systems are based on chips that contain a combination of general-purpose processors and application-specific accelerators, such as video decoders and encryption/decryption engines.

This trend shows the importance of a reliable, high-performance on-chip communication architecture that must be carefully designed so as not to become a bottleneck. Pasricha and Dutt’s book arrived at the right time to provide students, researchers, and designers with a comprehensive overview of architectural alternatives, design methodologies, and evaluation techniques for on-chip interconnects.

The book starts by showing how chip design problems are shifting from computation to communication, and uses examples of recent processors, such as IBM Cell, to make its point. Then, it dedicates several chapters to its core topic--on-chip buses. It covers the basic architectural concepts; industry standards such as AMBA, CoreConnect, and STBus; and a number of less conventional architectures, including asynchronous, code division multiple access (CDMA)-based, and dynamically reconfigurable buses.

Besides explaining architectural alternatives, the authors put special emphasis on the steps that must be taken from specification to implementation, to verification of on-chip buses. Models for performance, power consumption, and thermal dissipation are covered in detail, and the description of their integration with on-chip communication synthesis frameworks provides the reader with a good insight into the tradeoffs faced when choosing a particular bus implementation.

The final chapters address on-chip communication architectures that are still being researched. Networks-on-chip, which are somewhat more mature and already have commercially available implementations, have a dedicated chapter, while another chapter covers emerging technologies, such as optical, radio frequency (RF)/wireless, and carbon nanotube interconnects.

This is the first book about on-chip communications that successfully combines the didactic approach of a textbook with comprehensive state-of-the-art coverage that is typical of research surveys. It can be used as a reference by researchers and designers of communication-centric chips, and is well suited for undergraduate and graduate courses.