The fabrication costs of integrated circuits (IC) are extremely high. Multiproject wafers (MPW) are used to integrate, onto microelectronics wafers, a number of different IC designs from various teams, including designs from private firms, students, and academic researchers. This paper discusses several methods for the placement of chips in a reticle for MPW fabrication. Wu et al. introduce the MPW problem and provide a brief summary of the existing works in this area.

The MPW problem is formulated as a reticle floorplanning problem for a given set of N chips, where the desired production volumes for each chip are given. The objectives include: maximizing the compatibility of the chips within each reticle; minimizing the wafer requirements; and minimizing the dimension of each reticle, or restricting it within a specified value.

The work is primarily based on the concept of volume-driven compatibility optimization (VOCO), and attempts, simultaneously, to maximize the compatibility among the chips with large production volume requirements and minimize the reticle dimension. (Compatibility among chips is expressed in the form of side-to-side dicing constraints.)

Three different methods for the constrained reticle floorplanning are proposed. The first, a mixed-integer linear programming (MILP) method based on VOCO, considers the constraints on the placement of chips, as well as dicing lines and the related compatibility of chips with the objective function given by the concept of VOCO. The second method, a B*-tree-based floorplanning method with VOCO, is basically a B*-tree-based compact floorplanning superposed with VOCO. The third method is an improved hierarchical quadrisection floorplanning method with VOCO. The proposed hierarchical quadrisection method provides a better upper bound on the number of wafers utilized, and is the basis of a simulated annealing-based floorplanner.

The quality of the proposed methods is evaluated with detailed experimental results. The tables indicate that the proposed methods are better than some recent MPW methods, particularly in terms of minimizing wafer utilization.