This book describes a tool called ANDY used in conjunction with VLSI tools in use at California Institute of Technology. The author studies the power delay tradeoffs for NMOS circuits. The problem is well defined, and the book deals with a very specialized topic of interest to specialists in the field. It is not meant to be a typical classroom text, although the ideas stressed therein could be applied in the early design phase.

The goal is automated performance optimization. This is accomplished by resizing the transistors, laying them out, and repeating the cycle if the loads driven by the transistors have changed. The author emphasizes that this is a rapidly converging cycle, which seems to be true since the percentage change in the newly resized transistors keeps on decreasing.

Limitations of the technique are discussed in Chapter 6. One of the main problems is the inability to handle non-tree type pull down structures. Even the sorted path optimization technique should be taken with a grain of salt. ANDY uses electrical locality and optimization with respect to a set of inviolate rules. Fanout factor and minimum device size rules apply.

This is one of the few books relating to optimization techniques. The references are adequate. The book should prove to be an excellent reference for engineers interested in the performance of custom integrated circuits.