Computing Reviews
Today's Issue Hot Topics Search Browse Recommended My Account Log In
Review Help
Search
Inside solid state drives (SSDs)
Micheloni R., Marelli A., Eshghi K., Springer Publishing Company, Incorporated, Dordrecht, the Netherlands, 2013. 399 pp.  Type: Book (978-9-400751-45-3)
Date Reviewed: Jul 10 2013

Few areas in computing hardware have seen a surge in advancement comparable to what the field of solid state drives (SSDs) is currently experiencing. Until recently, disk storage enjoyed only small incremental improvements while processing power grew exponentially. The arrival of mass market SSDs is changing not only the way we design systems, but also how we use them. With access times now two orders of magnitude better than traditional hard disk drives (HDDs), change is inevitable. However, an SSD cannot be thought of as just a faster disk drive. SSDs work on fundamentally different principles; the more we know about them, the better we can take advantage of the potential they provide. This collection of chapters written by many different authors aims to enlighten the reader on all aspects of SSDs.

The first chapter provides an overview of the SSD marketplace. It plots the history and provides projections for revenue, reliability, and performance. The second chapter focuses on architecture. It explains flash memory and the memory controller, and includes a brief overview of wear leveling, garbage collection, and error correction. This chapter then diverges into why the PCI Express interface is a superior interface for SSDs. Chapter 3 compares the serial attached SCSI (SAS) and serial ATA (SATA) interfaces and explains how they relate to enterprise- versus consumer-focused products. In chapter 4, the authors discuss combining flash memories with HDDs, combining different types of flash memory into the same SSD, and combining different types of nonvolatile memories together.

From this point on, the chapters become significantly more complex. Chapter 5 describes NAND flash technology. It explains the concept of the floating gate and how charge can be trapped between the memory transistor channel and the active gate electrode. The chapter also describes the memory cell using a capacitive coupling model and the electron tunneling process during the program/erase cycles. The authors explain how to read off the stored voltage level for both single-level cells (SLCs) and multi-level cells (MLCs). This chapter ends with a detailed discussion on how the industry has been able to shrink the gate size far beyond the limits of direct optical lithography, and the multitude of technical problems that have ensued from that accomplishment.

Chapter 6 takes the reader through the next step, combining individual memory cells into usable semiconductor chips. It starts with a description of the different device interfaces, explains how each impacts the microcontroller, and describes how the microcontroller talks to the flash chips using the double data rate (DDR) interface made common by memory devices. The bulk of the chapter is dedicated to the voltage sensing technology that identifies the bit (or bits) stored in each cell, and it concludes with a discussion of the various methods used to efficiently generate the high voltage levels required during cell programming.

Chapter 7 presents a collection of designs and ideas for improving various aspects of an SSD. The author describes a selective bit line pre-charge scheme that can be used to significantly reduce power consumption when combined with another scheme for adjusting the source line during programming. The concept of power saving is extended with details on interleaving access to multiple chips and a proposal for an adaptive voltage generator for 3D SSDs. Chapter 8 is all about reliability, endurance, and data retention. The chapter looks at improving system-level reliability through RAID (redundant array of independent disks) systems and volatile memory-based caching. Solutions to power failure scenarios are also discussed. The most useful part of this chapter, however, is its step-by-step explanation of the industry-standardized reliability testing of SSDs.

To ensure that some sectors on an SSD do not wear out through excessive updates to their data (think of a log file), effective wear leveling is required; chapter 9 expands on this issue. The authors present two schemes and case studies that show its effectiveness. Chapter 10, the first of two chapters on error-correcting codes, addresses BCH, the more common error-correcting code (named after its inventors). Jumping right into information theory with 18 definitions and almost as many theorems, the authors cover decoding failures, detection properties, and weight estimation techniques for a number of BCH codes. Chapter 11 looks at the newer low-density parity-check (LDPC) code, starting with an explanation of theoretical channel capacity and the channel coding theorem. A description of LDPC code construction is followed by a step-by-step explanation of the belief propagation decoder and a brief overview of three reduced-complexity decoders.

Chapter 12 covers security and shows how encryption can be used to ensure data safety, while chapter 13 demonstrates how NAND flash memory can be combined with resistive random access memory (ReRAM) to improve performance, reliability, and energy consumption.

Given that this is a collection of independently written chapters, it is hard to identify a target readership. Some chapters are accessible to the public at large, while others require an understanding of electrical band diagrams, semiconductor manufacturing processes, or some level of information theory. However, if you are interested in how SSDs really work, this may be the book you are looking for.

More reviews about this item: Amazon

Reviewer:  Bernard Kuc Review #: CR141348 (1309-0760)
Bookmark and Share
  Reviewer Selected
Editor Recommended
Featured Reviewer
 
 
General (B.3.0 )
 
 
Files (E.5 )
 
Would you recommend this review?
yes
no
Other reviews under "General": Date
Memristor based computation-in-memory architecture for data-intensive applications
Hamdioui S., Xie L., Nguyen H., Taouil M., Bertels K., Corporaal H., Jiao H., Catthoor F., Wouters D., Eike L., van Lunteren J.  DATE 2015 (Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, Grenoble, France,  Mar 9-13, 2015) 1718-1725, 2015. Type: Proceedings
Sep 23 2015
GPU concurrency: weak behaviours and programming assumptions
Alglave J., Batty M., Donaldson A., Gopalakrishnan G., Ketema J., Poetzl D., Sorensen T., Wickerson J.  ASPLOS 2015 (Proceedings of the 20th International Conference on Architectural Support for Programming Languages and Operating Systems, Istanbul, Turkey,  Mar 14-18, 2015) 577-591, 2015. Type: Proceedings
Jul 16 2015
Simple memory machine models for GPUs
Nakano K.  International Journal of Parallel, Emergent and Distributed Systems 29(1): 17-37, 2014. Type: Article
Dec 27 2013
more...

E-Mail This Printer-Friendly
Send Your Comments
Contact Us
Reproduction in whole or in part without permission is prohibited.   Copyright © 2000-2019 ThinkLoud, Inc.
Terms of Use
| Privacy Policy