Computing Reviews
Today's Issue Hot Topics Search Browse Recommended My Account Log In
Review Help
Search
Reconfigurable networks-on-chip
Chen S., Lan Y., Tsai W., Hu Y., Springer Publishing Company, Incorporated, New York, NY, 2011. 216 pp.  Type: Book (978-1-441993-40-3)
Date Reviewed: Jul 24 2012

As the density of very large-scale integration (VLSI) increases, on-chip communications are required to accommodate the data exchange between heterogeneous functional elements on a single die. Traditional bus-based communication schemes cannot keep up with the ever more stringent requirements of future system-on-chip (SoC) architectures because they lack scalability and predictability. To meet the design challenges of next generation systems, a network-on-chip (NoC) architecture has been proposed to address the complex problem of on-chip communication and provide a structured and scalable interconnection architecture. This monograph reviews the fundamental theories, architectures, algorithms, and state-of-the-art development for NoC.

The book begins with an overview of the communication-centric design for multi-processor system-on-chip (MP-SoC) and conventional NoC architectures, followed by an extended introduction to the design methodology of NoC. The book concludes with a case study of bidirectional NoC (BiNoC) architecture.

Communication-centric design for MP-SoC is evaluated in terms of the advantages and disadvantages of the traditional bus-based communication schemes. The main disadvantage of bus-based communication schemes is that “the average communication bandwidth of each processing element is in inverse proportion to the total number of [Internet protocol, IP] cores in a system. This [fact] makes a bus-based architecture inherently not scalable for a complex system in ... MP-SoC design.” Because of this, an NoC architecture, with physical, network, and application layers, has been proposed to provide high throughput, low latency, and reliable global communication services to heterogeneous components on the same chip.

The section on conventional NoC architecture describes typical NoC network topology, mesh topology, the structure of an NoC router, the flow control mechanism, routing and medium access control (also known as arbitration), and quality of service (QoS) control. This section also briefly addresses reliability design and energy-aware task scheduling.

The extended introduction to the NoC design methodology covers techniques for high-performance NoC routing, performance-energy tradeoffs for NoC reliability, and energy-aware task scheduling. The crucial issue in routing strategies concerns the flexible and efficient use of the available routing resources to enhance routing adaptivity and to avoid deadlock and livelock in routing. The energy consumption issue is extensively explored in this part because on-chip global communications use more energy. Since voltage swings have been reduced with low power designs, the reliability of on-chip communications can be affected by environmental noise. To deal with the reliability issue, error detection techniques and retransmission methods are adopted. The energy consumption is an important issue when addressing performance-energy tradeoffs in the design of these techniques. Methods for constraining the energy consumption are identified in the form of available time slacks in the processing elements (PEs) in multiple-processor chips.

The BiNoC architecture can further improve communication performance. In a BiNoC, each communication channel can be “dynamically reconfigured to transmit ... in either direction.” The dynamic reconfiguration adds flexibility to achieve better bandwidth utilization and low packet latency. The real challenge in designing a BiNoC is to “devise a distributed channel-direction control protocol that ... [meets certain] performance criteria.” The section on BiNoc also covers the issues of QoS, fault tolerance, and energy-aware application mapping.

Overall, this monograph provides an in-depth, academic introduction to the design methodology of NoC architecture. It should not be treated as a tutorial for using commercial NoC products in various applications. It is suitable for academic researchers and professionals working with NoC. For the general audience, the interesting parts are those that don’t include discussions on energy consumption. Moreover, the general audience is more interested in how to use NoC products in their applications. Thus, they will benefit from a different book that focuses more on this.

Reviewer:  Jun Liu Review #: CR140461 (1211-1083)
Bookmark and Share
 
Interconnections (Subsystems) (B.4.3 )
 
 
Performance Analysis And Design Aids (B.8.2 )
 
 
Reliability, Testing, And Fault-Tolerance (B.8.1 )
 
Would you recommend this review?
yes
no
Other reviews under "Interconnections (Subsystems)": Date
Parallel programming model for the Epiphany many-core coprocessor using threaded MPI
Ross J., Richie D., Park S., Shires D.  Microprocessors & Microsystems 43(C): 95-103, 2016. Type: Article
Aug 29 2016
HPC in big data age: an evaluation report for Java-based data-intensive applications implemented with Hadoop and OpenMPI
Cheptsov A.  EuroMPI/ASIA 2014 (Proceedings of the 21st European MPI Users’ Group Meeting, Kyoto, Japan,  Sep 9-12, 2014) 175-180, 2014. Type: Proceedings
Nov 25 2014
Networks on chip
Jantsch A., Tenhunen H.,  Kluwer Academic Publishers, Norwell, MA, 2003. 312 pp. Type: Book (9781402073922)
Dec 15 2003
more...

E-Mail This Printer-Friendly
Send Your Comments
Contact Us
Reproduction in whole or in part without permission is prohibited.   Copyright © 2000-2017 ThinkLoud, Inc.
Terms of Use
| Privacy Policy