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Browse All Reviews > Computer Systems Organization (C) > Processor Architectures (C.1) > Multiple Data Stream Architectures (Multiprocessors) (C.1.2) > Pipeline Processors (C.1.2...)
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1-4 of 4
Reviews about "Pipeline Processors (C.1.2...)":
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Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers
Sohi G. IEEE Transactions on Computers 39(3): 349-359, 1990. Type: Article
The author considers two issues in this paper dealing with pipelined computers: data dependencies and precise interrupts. A companion issue, not focused on, is branch instructions. For all three issues, execution speed is the author&am...
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May 1 1992 |
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CPC (Cyclic Pipeline Computer)-an Architecture Suited for Josephson and Pipelined-Memory Machines
Shimizu K., Goto E., Ichikawa S. IEEE Transactions on Computers 38(6): 825-832, 1989. Type: Article
Processors constructed with Josephson logic are highly suited for pipelining because each basic logic device acts as a latch. Pipelines in traditional architectures are typically slowed down by latch-times required by the pipeline&...
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Jul 1 1990 |
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Implementing Precise Interrupts in Pipelined Processors
Smith J., Pleszkun A. IEEE Transactions on Computers 37(5): 562-573, 1988. Type: Article
The question of how to handle interrupts in pipelined processors is one of the most exciting design and engineering decisions, especially when sequential architectures are used together with pipelined implementations. Because the pipel...
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Apr 1 1989 |
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Synchronizing large VLSI processor arrays
Fisher A., Kung H. IEEE Transactions on Computers 34(9): 734-740, 1985. Type: Article
This paper is concerned with the problems associated with clock distribution in large VLSI processor arrays. The authors present two models of clock skew and evaluate the effectiveness of several array structures with respect to these ...
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Aug 1 1986 |
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