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Browse All Reviews > Computer Systems Organization (C) > Processor Architectures (C.1) > Multiple Data Stream Architectures (Multiprocessors) (C.1.2) > Array And Vector Processors (C.1.2...)
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1-10 of 20
Reviews about "Array And Vector Processors (C.1.2...)":
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Date Reviewed |
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k-top scoring pair algorithm for feature selection in SVM with applications to microarray data classification
Yoon S., Kim S. Soft Computing 14(2): 151-159, 2009. Type: Article
The classification of gene data is one of the most interesting areas in biomedical signal processing. The efficiency of the classification algorithm depends mainly on feature extraction, feature selection, and the classification mechan...
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Mar 1 2010 |
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Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform
Milovanović E., Milovanović I., Bekakos M., Tselepis I. The Journal of Supercomputing 40(1): 49-66, 2007. Type: Article
The shortest path problem in graph theory is an abstraction of many practical problems; it arises in many applications in network routing and distributed computing. A regular linear systolic array for computing the all-pairs shortest p...
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Jul 18 2007 |
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Optimizing memory usage in the polyhedral model
Quilleré F., Rajopadhye S. ACM Transactions on Programming Languages and Systems 22(5): 773-815, 2000. Type: Article
Quilleré and Rajopadhye address the problem of memory size optimization when compiling Systems of Affine Recurrence Relations (SARE), defined over polyhedral index domains. The formalism to do this, detailed in the paper, is r...
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Nov 1 2001 |
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Multirate VLSI arrays and their synthesis
Lenders P., Rajopadhye S. IEEE Transactions on Software Engineering 23(9): 515-529, 1997. Type: Article
Multirate arrays are an extension of the idea of systolic arrays in which different data streams can propagate at different rates, that is, using different clock ticks. Applications in signal and image processing can often be implement...
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Feb 1 1998 |
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Parallel processing in cellular arrays
Fet Y., John Wiley & Sons, Inc., New York, NY, 1995. Type: Book (9780471954095)
Cellular computation in the form of specialized distributed functional structures is the focus of this book. In addition to presenting distributed functional structures designed to implement a variety of operations, the book discusses ...
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Feb 1 1997 |
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Parallel and vector computing
Leiss E., McGraw-Hill, Inc., New York, NY, 1995. Type: Book (9780070376922)
This exquisite book offers practical, sensible, and rather witty coverage of parallel and vector computers. It does not explain architecture in detail, but contrasts the advantages and shortcomings of various parallel and vector archit...
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Sep 1 1996 |
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Survey on array processors: survey report #41
Miller R. (ed), 1988. Type: Book
Array processors are generally used as attached processors to increase the throughput of a host computer. As defined in this survey, array processors are 32-bit scalar machines performing high-speed mathematical computations over strea...
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Mar 1 1991 |
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A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays
Chean M., Fortes J. Computer 23(1): 55-69, 1990. Type: Article
Chean and Fortes introduce a taxonomy of reconfiguration techniques for fault-tolerant processor arrays and discuss their distinguishing characteristics. They do not exhaustively survey previously proposed reconfiguration schemes. Inst...
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Dec 1 1990 |
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Vector Pipelining, Chaining, and Speed on the IBM 3090 and Cray X-MP
Cheng H. Computer 22(9): 31-42, 44, 46, 1989. Type: Article
Cheng attempts to characterize the performance of 24 simple vectorizable FORTRAN loops on two vector supercomputers. Cheng collected the data scientifically and compares the two machines. This paper is intended for several audiences: v...
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Oct 1 1990 |
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On Fault-Tolerant Structure, Distributed Fault-Diagnosis, Reconfiguration, and Recovery of the Array Processors
Hosseini S. IEEE Transactions on Computers 38(7): 932-942, 1989. Type: Article
As the number of processors and interconnecting links in a multiprocessor increases, the risk of hardware failure grows. Hosseini’s paper addresses fault tolerance for parallel processing architectures. It explains a new inte...
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Oct 1 1990 |
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