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Reviews about "Reliability And Testing (B.7.3)":
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DFM evaluation using IC diagnosis data Blanton R., Wang F., Xue C., Nag P., Xue Y., Li X. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36(3): 463-474, 2017. Type: Article
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Parallel Signature Analysis Design with Bounds on Aliasing Saxena N., McCluskey E. IEEE Transactions on Computers 46(4): 425-438, 1997. Type: Article
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AVPGEN--a test generator for architecture verification Chandra A., Iyengar V., Jameson D., Jawalekar R., Nair I., Rosen B., Mullen M., Yoon J., Armoni R., Geist D., Wolfsthal Y. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3(2): 188-200, 1995. Type: Article
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Fault covering problems in reconfigurable VLSI systems Libeskind-Hadas R., Hasan N., Cong J., McKinley P., Liu C., Kluwer Academic Publishers, Norwell, MA, 1992. Type: Book (9780792392316)
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Silicon compilation of hierarchical control sections with unified BIST testability Nicolaidis M., Torki K., Jerraya A., Courtois B. (ed) Microprocessors & Microsystems 15(5): 257-269, 1991. Type: Article
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Built-In Testing of Integrated Circuit Wafers Rangarajan S., Fussell D., Malek M. IEEE Transactions on Computers 39(2): 195-205, 1990. Type: Article
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Selecting test methodologies for PLAs and random logic modules in VLSI circuits--an expert systems approach Bhawmik S., Narang V., Chaudhuri P. Integration, the VLSI Journal 7(3): 267-281, 1989. Type: Article
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