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Reviews about "Design Aids (B.5.2)":
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Date Reviewed |
Design optimization for security- and safety-critical distributed real-time applications
Jiang W., Pop P., Jiang K. Microprocessors & Microsystems 52 401-415, 2017. Type: Article
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Dec 13 2017 |
Fast design exploration for performance, power and accuracy tradeoffs in FPGA-based accelerators
Ulusel O., Nepal K., Bahar R., Reda S. ACM Transactions on Reconfigurable Technology and Systems 7(1): 1-22, 2014. Type: Article
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Jun 3 2014 |
FPGA technology mapping with encoded libraries and staged priority cuts
Kennings A., Vorwerk K., Kundu A., Pevzner V., Fox A. ACM Transactions on Reconfigurable Technology and Systems 4(4): 1-17, 2011. Type: Article
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Jun 11 2012 |
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
Bombieri N., Fummi F., Pravadelli G. ACM Transactions on Design Automation of Electronic Systems 13(3): 1-22, 2008. Type: Article
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Sep 18 2008 |
Writing testbenches: functional verification of HDL models (2nd ed.)
Bergeron J., Kluwer Academic Publishers, Norwell, MA, 2003. Type: Book (9781402074011)
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Nov 16 2004 |
Symbolic RTL simulation
Kölbl A., Kukula J., Damiano R. Design automation (Proceedings of the 38th conference, Las Vegas, Nevada, United States, 47-52, 2001. Type: Proceedings
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Dec 1 2001 |
Electronic chips & systems design languages
Mermet J. Kluwer Academic Publishers, Norwell, MA, 2001. Type: Divisible Book
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Sep 1 2001 |
more...
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