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	ACM Transactions on Architecture and Code Optimization ACM Press         Options: Date Reviewed Title Author Publisher Published Date Descending Order Ascending Order     1-10 of 38 reviews Date Reviewed      Vitruvius+: an area-efficient RISC-V decoupled vector coprocessor for high performance computing applications Minervini F., Palomar O., Unsal O., Reggiani E., Quiroga J., Marimon J., Rojas C., Figueras R. ACM Transactions on Architecture and Code Optimization 20(2): 1-25, 2023.  Type: Article Vector processors had their heyday in the 1980s, before classical supercomputers were mostly replaced by multiprocessors. Today, however, vector processors are experiencing a renaissance: their efficient exploitation of data-level parallelism has ... Aug 2 2023   Flextended tiles: a flexible extension of overlapped tiles for polyhedral compilation Zhao J., Cohen A. ACM Transactions on Architecture and Code Optimization 16(4): 1-25, 2019.  Type: Article This paper describes a proposal for implementing “overlapped tiling in a general-purpose polyhedral compilation framework,” namely the polyhedral parallel code generator (PPCG) compiler. The technique improves the p... Jun 13 2020   Dual-page checkpointing: an architectural approach to efficient data persistence for in-memory applications Wu S., Zhou F., Gao X., Jin H., Ren J. ACM Transactions on Architecture and Code Optimization 15(4): 1-27, 2019.  Type: Article In-memory computing is one of the most important paradigm shifts in today’s processing models. This interesting and innovative approach is possible because not only do we have new ideas on how to perform data processing witho... Nov 1 2019   Coordinated CTA combination and bandwidth partitioning for GPU concurrent kernel execution Lin Z., Dai H., Mantor M., Zhou H. ACM Transactions on Architecture and Code Optimization 16(3): 1-27, 2019.  Type: Article The high throughput of processors (or, more broadly, computers) has always been a key issue in computer systems architecture. For many years, the most dominant way to increase throughput was to increase the processor clock frequency. B... Oct 25 2019   Data-driven concurrency for high performance computing Matheou G., Evripidou P. ACM Transactions on Architecture and Code Optimization 14(4): 1-26, 2017.  Type: Article, Reviews: (2 of 2) While in procedural parallel programming with multithreading lemmas, the synchronization of the sequences of parallel execution of tasks is important to quick job execution, the data-driven method draws a new pattern. By passing synchr... Oct 8 2018    Data-driven concurrency for high performance computing Matheou G., Evripidou P. ACM Transactions on Architecture and Code Optimization 14(4): 1-26, 2017.  Type: Article, Reviews: (1 of 2) Fine-grained dataflow computing creates circumstances that technologies, particularly hardware technologies, have difficulty handling. However, techniques like coarsening computational grain and substituting software for hardware, as d... Aug 30 2018   Compiler-assisted loop hardening against fault attacks Proy J., Heydemann K., Berzati A., Cohen A. ACM Transactions on Architecture and Code Optimization 14(4): 1-25, 2017.  Type: Article The problem to solve is the following: the uncontrolled development of the Internet of Things (IoT) results in personal data being handled by a huge variety of devices, which do not satisfy the safety conditions considered mandatory in... Jun 1 2018   Improving loop dependence analysis Jensen N., Karlsson S. ACM Transactions on Architecture and Code Optimization 14(3): 1-24, 2017.  Type: Article Research on multicore utilization embraces three major categories of topics: investigations regarding the issues of multicore interaction functionality, operating system affairs and compilers, and programming language concerns. The pap... Dec 7 2017   Fine-grain power breakdown of modern out-of-order cores and its implications on Skylake-based systems Haj-Yihia J., Yasin A., Asher Y., Mendelson A. ACM Transactions on Architecture and Code Optimization 13(4): Article No. 56, 2016.  Type: Article Extreme-scale data centers and supercomputers draw many megawatts of power to function. By today’s standards, drawing one megawatt of power roughly costs $1 million; hence, reduced power consumption is critical for these syst... Aug 28 2017   Exploiting hierarchical locality in deep parallel architectures Anbar A., Serres O., Kayraklioglu E., Badawy A., El-Ghazawi T. ACM Transactions on Architecture and Code Optimization 13(2): 1-25, 2016.  Type: Article Locality awareness in programs can be used to improve their execution performance on parallel computers. Modern parallel computers have many levels of parallelism; many cores on a chip and many chips in a node are examples. Locality aw... Aug 26 2016       Display 510152550100 per column
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