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Kavalipati, Paparao

California
 
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Paparao Kavalipati is a software developer and consultant on electronics design automation (EDA) products with expertise in formal verification, logic synthesis, and related technologies. He is currently employed at Tabula Inc. Prior to that, he was a member of the R&D team at major EDA vendors like Mentor Graphics Corp. and Synopsys Inc.

With more than 18 years of experience in the industry, Paparao delivered new features and improvements for a range of products that include programmable logic devices, timing constraint verification, assertion synthesis, RTL compilation, model checking, equivalence checking, and simulation.

Paparao also offers development services and solutions to startup companies.  Working as an independent consultant, Paparao designed and developed a hybrid satisfiability engine for the verification of false paths and multi-cycle paths by formulating them as safety properties.

At Mentor Graphics, Paparao designed and implemented a high-level optimizer for assertion expressions, which benefited the 0in formal product in quickly verifying complex properties written in SVA and PSL. Paparao also contributed to the R&D efforts on low-power design verification, and synthesizing multi-clock SVA. At Synopsys, Paparao crafted various coding refinements to Magellan, Formality, and Scirocco products, covering a broad scope of projects on RTL synthesis, data path equivalence, and simulation speed-up.

His interests span a wide spectrum starting from fundamental algorithms, optimization methods, compilers, and automata theory as embedded in the art of electronics design and verification. Being an industrial researcher, he focuses on theoretical concepts that can relate well to pragmatic applications.

Attracted by the opportunities that Computing Reviews provides for continued learning, Paparao has been volunteering as a reviewer since 2008 and brings a practitioner’s point of view to the articles and books that he reads. He looks forward to keeping in touch with the technological and academic advances while rendering more reviews in the future.

Paparao received his master’s degree from the Indian Institute of Science, Bangalore, in 1996.

 
 
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1
- 6 of 6 reviews

   
  Cryptographic and information security approaches for images and videos
Ramakrishnan S., CRC Press, Inc., Boca Raton, FL, 2019. 986 pp.  Type: Book (978-1-138563-84-1)

Cryptography is the art of securing communications transmitted through insecure channels. It consists of mechanisms to keep the data confidential by preventing access to unapproved individuals, maintaining the integrity of the data thr...

Nov 26 2019  
   Data stream management: processing high-speed data streams
Garofalakis M., Gehrke J., Rastogi R., Springer International Publishing, New York, NY, 2016.  Type: Book (9783540286073)

Efficient data management is the distinguishing factor for the success of computer applications. Traditional software made use of querying and updating persistent datasets saved in a stable storage format. With growing usage, increased...

Jan 5 2017  
   Practical C++ financial programming
Oliveira C., Apress, New York, NY, 2015. 396 pp.  Type: Book (978-1-430267-15-7), Reviews: (1 of 2)

Financial programs form a large percentage of C++ applications in the software industry. Starting from tracking fixed income investments and equities, up to option pricing and portfolio optimization, the problems in the domain, and the...

Nov 11 2015  
   Finite state machines in hardware: theory and design (with VHDL and SystemVerilog)
Pedroni V., The MIT Press, Cambridge, MA, 2013. 352 pp.  Type: Book (978-0-262019-66-8)

Digital circuits where the output values depend on the state of the system are called sequential. A finite state machine (FSM) is a modeling technique for sequential circuits. At any point of its operation, the machine will be in one o...

Jul 10 2014  
  Circuit design and simulation with VHDL
Pedroni V., The MIT Press, Cambridge, MA, 2010. 680 pp.  Type: Book (978-0-262014-33-5)

Just as SystemVerilog began gaining popularity as a hardware description language (HDL), the IEEE, in 2008, standardized a new version of VHSIC HDL (VHDL), with significant enhancements. This second edition covers the new features very...

Oct 21 2011  
   An approximate algorithm for the multiple constant multiplications problem
Aksoy L., Gunes E.  Integrated circuits and system design (Proceedings of the Twenty-first Annual Symposium on Integrated Circuits and System Design, Gramado, Brazil, Sep 1-4, 2008) 58-63, 2008.  Type: Proceedings

Efficient synthesis of register transfer level (RTL) arithmetic operations is critical for the performance of data-processing hardware. Multipliers are crucial among all such operators. Multiplication of a variable with a single intege...

Nov 19 2008  
 
 
 
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