Computing Reviews
Today's Issue Hot Topics Search Browse Recommended My Account Log In
Browse by topic Browse by titles Authors Reviewers Browse by issue Browse Help
Search
 
Kavalipati, Paparao

California
 
   Featured Reviewer
   Reader Recommended
   Reviewer Selected
   Highlighted
Follow this Reviewer
 
 
 

Paparao Kavalipati is a software developer and consultant on electronics design automation (EDA) products with expertise in formal verification, logic synthesis, and related technologies. He is currently employed at Tabula Inc. Prior to that, he was a member of the R&D team at major EDA vendors like Mentor Graphics Corp. and Synopsys Inc.

With more than 18 years of experience in the industry, Paparao delivered new features and improvements for a range of products that include programmable logic devices, timing constraint verification, assertion synthesis, RTL compilation, model checking, equivalence checking, and simulation.

Paparao also offers development services and solutions to startup companies.  Working as an independent consultant, Paparao designed and developed a hybrid satisfiability engine for the verification of false paths and multi-cycle paths by formulating them as safety properties.

At Mentor Graphics, Paparao designed and implemented a high-level optimizer for assertion expressions, which benefited the 0in formal product in quickly verifying complex properties written in SVA and PSL. Paparao also contributed to the R&D efforts on low-power design verification, and synthesizing multi-clock SVA. At Synopsys, Paparao crafted various coding refinements to Magellan, Formality, and Scirocco products, covering a broad scope of projects on RTL synthesis, data path equivalence, and simulation speed-up.

His interests span a wide spectrum starting from fundamental algorithms, optimization methods, compilers, and automata theory as embedded in the art of electronics design and verification. Being an industrial researcher, he focuses on theoretical concepts that can relate well to pragmatic applications.

Attracted by the opportunities that Computing Reviews provides for continued learning, Paparao has been volunteering as a reviewer since 2008 and brings a practitioner’s point of view to the articles and books that he reads. He looks forward to keeping in touch with the technological and academic advances while rendering more reviews in the future.

Paparao received his master’s degree from the Indian Institute of Science, Bangalore, in 1996.

 
 
Options:
Date Reviewed  
 
1
- 2 of 2 reviews

   
   The Merino-Welsh conjecture holds for series-parallel graphs
Noble S., Royle G. European Journal of Combinatorics 3824-35, 2014.  Type: Article

Orientation is an assignment of direction to each edge of an undirected graph. When none of the directed edges is in a cycle, the orientation is called acyclic. When every directed edge is in some cycle, the orientation is called total...

Aug 20 2014  
   An approximate algorithm for the multiple constant multiplications problem
Aksoy L., Gunes E.  Integrated circuits and system design (Proceedings of the Twenty-first Annual Symposium on Integrated Circuits and System Design, Gramado, Brazil, Sep 1-4, 2008) 58-63, 2008.  Type: Proceedings

Efficient synthesis of register transfer level (RTL) arithmetic operations is critical for the performance of data-processing hardware. Multipliers are crucial among all such operators. Multiplication of a variable with a single intege...

Nov 19 2008  
 
 
   
Send Your Comments
Contact Us
Reproduction in whole or in part without permission is prohibited.   Copyright 1999-2024 ThinkLoud®
Terms of Use
| Privacy Policy