Computing Reviews
Today's Issue Hot Topics Search Browse Recommended My Account Log In
Review Help
Search
A differential equation for placement analysis
Christie P.  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (6): 913-921, 2001. Type: Article
Date Reviewed: Jun 21 2002

Most models for on-chip wire length estimation involve two tasks: the enumeration of two-terminal net placement sites, and the population of these sites using a function derived from Rent’s rule. Rent’s rule estimates the number of boundary-crossing wires using the number of cells enclosed by the boundary. As the number of cells becomes comparable to the total number of cells in the circuit, the estimation becomes worse.

The author of this paper has derived a first-order differential equation to describe the relation between the number of boundary-crossing wires and the number of cells enclosed by the boundary, by considering the processes that generate and terminate boundary-crossing wires. The differential equation model accurately captures the “non-Rentian” deviations displayed in experimental data from a commercial placement tool. Using the differential model in wire length estimation also shows a better fit to the experimental data in region II of Rent’s graph.

The main contribution of this paper is the presentation of a method for using a first-order differential equation to describe the process of wires being generated or terminated through the boundary. A second contribution is the author’s demonstration that Rent’s rule is a special solution to the differential equation, given the condition that the number of cells in the boundary box is small compared to the total number of cells, and that the effect of pins is neglected. The proposed model helps to provide a better estimation for on-chip wire lengths.

Reviewer:  Baohua Wang Review #: CR126191 (0208-0430)
Bookmark and Share
 
Placement And Routing (B.7.2 ... )
 
 
General (B.7.0 )
 
Would you recommend this review?
yes
no
Other reviews under "Placement And Routing": Date
MaizeRouter: engineering an effective global router
Moffitt M.  ASP-DAC 2008 (Proceedings of the 2008 Asia and South Pacific Design Automation Conference, Seoul, Korea,  Jan 21-24, 2008) 226-231, 2008. Type: Proceedings
Apr 17 2009
The coming of age of (academic) global routing
Moffitt M., Roy J., Markov I.  Physical design (Proceedings of the 2008 International Symposium on Physical Design, Portland, Oregon,  Apr 13-16, 2008) 148-155, 2008. Type: Proceedings
Jun 12 2008
Hierarchical partitioning of VLSI floorplans by staircases
Majumder S., Sur-Kolay S., Bhattacharya B., Das S.  ACM Transactions on Design Automation of Electronic Systems 12(1): 7-es, 2007. Type: Article
Feb 6 2008
more...

E-Mail This Printer-Friendly
Send Your Comments
Contact Us
Reproduction in whole or in part without permission is prohibited.   Copyright © 2000-2017 ThinkLoud, Inc.
Terms of Use
| Privacy Policy