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	IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Educational Activities Department         Options: Date Reviewed Title Author Publisher Published Date Descending Order Ascending Order     1-10 of 49 reviews Date Reviewed     Using the minimum set of input combinations to minimize the area of local routing networks in logic clusters containing logically equivalent I/Os in FPGAs Ye A. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18(1): 95-107, 2010.  Type: Article This is a very good academic paper, but it contains little of practical value to most design teams. It shows that the area of local routing networks that connect cluster inputs to individual lookup table (LUT) inputs can be significant... Feb 8 2011   Automatic test generation for combinational threshold logic networks Gupta P., Zhang R., Jha N. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(8): 1035-1045, 2008.  Type: Article Two nanoscale devices that implement threshold logic are resonant tunneling diodes (RTDs) and quantum cellular automata (QCA). A threshold logic gate (TLG) computes the sign of the weighted sum of its inputs, compared with a threshold.... Jun 12 2009   Dynamically configurable bus topologies for high-performance on-chip communication Sekar K., Lahiri K., Raghunathan A., Dey S. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(10): 1413-1426, 2008.  Type: Article Sekar et al. present FLEXBUS, a novel on-chip communication bus topology that can be configured to map components in a system-on-chip (SoC) design based on application traffic characteristics.... May 14 2009   A low-power reconfigurable logic array based on double-gate transistors Beckett P. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(2): 115-123, 2008.  Type: Article A reconfigurable architecture, based on double-gate (DG) transistor circuits, that could be suitable for implementing low-power reconfigurable logic arrays, targeting future nanoscale technologies, is discussed in this paper. The opera... Aug 27 2008   A methodology for transistor-efficient supergate design Kagaris D., Haniotakis T. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15(4): 488-492, 2007.  Type: Article Though well written, this paper addresses a very limited audience: those designing custom chips, in which chip area is the crucial parameter.... Feb 27 2008   Concurrent error detection in Reed-Solomon encoders and decoders Cardarilli G., Pontarelli S., Re M., Salsano A. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15(7): 842-846, 2007.  Type: Article Reed-Solomon (RS) error-correcting codes are able to detect and correct errors in transmission and storage systems and are used in a wide variety of commercial applications, such as DVD, worldwide interoperability for microwave access ... Jan 24 2008   Efficient testing of SRAM with optimized March sequences and a novel DFT technique for emerging failures due to process variations Chen Q., Mahmoodi H., Bhunia S., Roy K. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13(11): 1286-1295, 2005.  Type: Article Anyone interested in very large-scale integration (VLSI) circuit design, the effects of manufacturing process parameter variations, failure mechanisms in VLSI chips, fault modeling of chip failures, testing VLSI chips, design for test ... Oct 13 2006   A novel wavelet transform-based transient current analysis for fault detection and localization Bhunia S., Roy K. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13(4): 503-507, 2005.  Type: Article In this interesting paper, Bhunia and Roy present a novel integrated method for fault detection and localization, using wavelet transform-based IDD waveform analysis. The authors demonstrate that the wavelet transform has better sensit... Nov 29 2005   A dictionary-based en/decoding scheme for low-power data buses Lv T., Henkel J., Lekatsas H., Wolf W. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11(5): 943-951, 2003.  Type: Article With systems-on-a-chip (SOC) expected to exceed the one billion transistor milestone within the next few years, the authors seek a new coding strategy to reduce power consumption. This paper addresses the saturation of transistor chip ... Jun 18 2004   Low-leakage asymmetric-cell SRAM Azizi N., Najm F., Moshovos A. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11(4): 701-715, 2003.  Type: Article This work introduces a new cache (static random access memory (SRAM)) memory cell, composed of asymmetric transistors, and intended to reduce leakage current, and, consequently, power dissipation.... Mar 10 2004       Display 510152550100 per column
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